RTOS 1.0
stm32f423xx.h
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33#ifndef __STM32F423xx_H
34#define __STM32F423xx_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif /* __cplusplus */
39
43
47#define __CM4_REV 0x0001U
48#define __MPU_PRESENT 1U
49#define __NVIC_PRIO_BITS 4U
50#define __Vendor_SysTickConfig 0U
51#define __FPU_PRESENT 1U
52
56
60
65typedef enum
66{
67 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
68 NonMaskableInt_IRQn = -14,
69 MemoryManagement_IRQn = -12,
70 BusFault_IRQn = -11,
71 UsageFault_IRQn = -10,
72 SVCall_IRQn = -5,
73 DebugMonitor_IRQn = -4,
74 PendSV_IRQn = -2,
75 SysTick_IRQn = -1,
76 /****** STM32 specific Interrupt Numbers **********************************************************************/
77 WWDG_IRQn = 0,
78 PVD_IRQn = 1,
79 TAMP_STAMP_IRQn = 2,
80 RTC_WKUP_IRQn = 3,
81 FLASH_IRQn = 4,
82 RCC_IRQn = 5,
83 EXTI0_IRQn = 6,
84 EXTI1_IRQn = 7,
85 EXTI2_IRQn = 8,
86 EXTI3_IRQn = 9,
87 EXTI4_IRQn = 10,
88 DMA1_Stream0_IRQn = 11,
89 DMA1_Stream1_IRQn = 12,
90 DMA1_Stream2_IRQn = 13,
91 DMA1_Stream3_IRQn = 14,
92 DMA1_Stream4_IRQn = 15,
93 DMA1_Stream5_IRQn = 16,
94 DMA1_Stream6_IRQn = 17,
95 ADC_IRQn = 18,
96 CAN1_TX_IRQn = 19,
97 CAN1_RX0_IRQn = 20,
98 CAN1_RX1_IRQn = 21,
99 CAN1_SCE_IRQn = 22,
100 EXTI9_5_IRQn = 23,
101 TIM1_BRK_TIM9_IRQn = 24,
102 TIM1_UP_TIM10_IRQn = 25,
103 TIM1_TRG_COM_TIM11_IRQn = 26,
104 TIM1_CC_IRQn = 27,
105 TIM2_IRQn = 28,
106 TIM3_IRQn = 29,
107 TIM4_IRQn = 30,
108 I2C1_EV_IRQn = 31,
109 I2C1_ER_IRQn = 32,
110 I2C2_EV_IRQn = 33,
111 I2C2_ER_IRQn = 34,
112 SPI1_IRQn = 35,
113 SPI2_IRQn = 36,
114 USART1_IRQn = 37,
115 USART2_IRQn = 38,
116 USART3_IRQn = 39,
117 EXTI15_10_IRQn = 40,
118 RTC_Alarm_IRQn = 41,
119 OTG_FS_WKUP_IRQn = 42,
120 TIM8_BRK_TIM12_IRQn = 43,
121 TIM8_UP_TIM13_IRQn = 44,
122 TIM8_TRG_COM_TIM14_IRQn = 45,
123 TIM8_CC_IRQn = 46,
124 DMA1_Stream7_IRQn = 47,
125 SDIO_IRQn = 49,
126 TIM5_IRQn = 50,
127 SPI3_IRQn = 51,
128 UART4_IRQn = 52,
129 UART5_IRQn = 53,
130 TIM6_DAC_IRQn = 54,
131 TIM7_IRQn = 55,
132 DMA2_Stream0_IRQn = 56,
133 DMA2_Stream1_IRQn = 57,
134 DMA2_Stream2_IRQn = 58,
135 DMA2_Stream3_IRQn = 59,
136 DMA2_Stream4_IRQn = 60,
137 DFSDM1_FLT0_IRQn = 61,
138 DFSDM1_FLT1_IRQn = 62,
139 CAN2_TX_IRQn = 63,
140 CAN2_RX0_IRQn = 64,
141 CAN2_RX1_IRQn = 65,
142 CAN2_SCE_IRQn = 66,
143 OTG_FS_IRQn = 67,
144 DMA2_Stream5_IRQn = 68,
145 DMA2_Stream6_IRQn = 69,
146 DMA2_Stream7_IRQn = 70,
147 USART6_IRQn = 71,
148 I2C3_EV_IRQn = 72,
149 I2C3_ER_IRQn = 73,
150 CAN3_TX_IRQn = 74,
151 CAN3_RX0_IRQn = 75,
152 CAN3_RX1_IRQn = 76,
153 CAN3_SCE_IRQn = 77,
154 AES_IRQn = 79,
155 RNG_IRQn = 80,
156 FPU_IRQn = 81,
157 UART7_IRQn = 82,
158 UART8_IRQn = 83,
159 SPI4_IRQn = 84,
160 SPI5_IRQn = 85,
161 SAI1_IRQn = 87,
162 UART9_IRQn = 88,
163 UART10_IRQn = 89,
164 QUADSPI_IRQn = 92,
165 FMPI2C1_EV_IRQn = 95,
166 FMPI2C1_ER_IRQn = 96,
167 LPTIM1_IRQn = 97,
168 DFSDM2_FLT0_IRQn = 98,
169 DFSDM2_FLT1_IRQn = 99,
170 DFSDM2_FLT2_IRQn = 100,
171 DFSDM2_FLT3_IRQn = 101
172} IRQn_Type;
173
177
178#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
179#include "system_stm32f4xx.h"
180#include <stdint.h>
181
185
189
190typedef struct
191{
192 __IO uint32_t SR;
193 __IO uint32_t CR1;
194 __IO uint32_t CR2;
195 __IO uint32_t SMPR1;
196 __IO uint32_t SMPR2;
197 __IO uint32_t JOFR1;
198 __IO uint32_t JOFR2;
199 __IO uint32_t JOFR3;
200 __IO uint32_t JOFR4;
201 __IO uint32_t HTR;
202 __IO uint32_t LTR;
203 __IO uint32_t SQR1;
204 __IO uint32_t SQR2;
205 __IO uint32_t SQR3;
206 __IO uint32_t JSQR;
207 __IO uint32_t JDR1;
208 __IO uint32_t JDR2;
209 __IO uint32_t JDR3;
210 __IO uint32_t JDR4;
211 __IO uint32_t DR;
212} ADC_TypeDef;
213
214typedef struct
215{
216 __IO uint32_t CSR;
217 __IO uint32_t CCR;
218 __IO uint32_t CDR;
220} ADC_Common_TypeDef;
221
222
226
227typedef struct
228{
229 __IO uint32_t TIR;
230 __IO uint32_t TDTR;
231 __IO uint32_t TDLR;
232 __IO uint32_t TDHR;
233} CAN_TxMailBox_TypeDef;
234
238
239typedef struct
240{
241 __IO uint32_t RIR;
242 __IO uint32_t RDTR;
243 __IO uint32_t RDLR;
244 __IO uint32_t RDHR;
245} CAN_FIFOMailBox_TypeDef;
246
250
251typedef struct
252{
253 __IO uint32_t FR1;
254 __IO uint32_t FR2;
255} CAN_FilterRegister_TypeDef;
256
260
261typedef struct
262{
263 __IO uint32_t MCR;
264 __IO uint32_t MSR;
265 __IO uint32_t TSR;
266 __IO uint32_t RF0R;
267 __IO uint32_t RF1R;
268 __IO uint32_t IER;
269 __IO uint32_t ESR;
270 __IO uint32_t BTR;
271 uint32_t RESERVED0[88];
272 CAN_TxMailBox_TypeDef sTxMailBox[3];
273 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
274 uint32_t RESERVED1[12];
275 __IO uint32_t FMR;
276 __IO uint32_t FM1R;
277 uint32_t RESERVED2;
278 __IO uint32_t FS1R;
279 uint32_t RESERVED3;
280 __IO uint32_t FFA1R;
281 uint32_t RESERVED4;
282 __IO uint32_t FA1R;
283 uint32_t RESERVED5[8];
284 CAN_FilterRegister_TypeDef sFilterRegister[28];
285} CAN_TypeDef;
286
290
291typedef struct
292{
293 __IO uint32_t DR;
294 __IO uint8_t IDR;
295 uint8_t RESERVED0;
296 uint16_t RESERVED1;
297 __IO uint32_t CR;
298} CRC_TypeDef;
299
303typedef struct
304{
305 __IO uint32_t FLTCR1;
306 __IO uint32_t FLTCR2;
307 __IO uint32_t FLTISR;
308 __IO uint32_t FLTICR;
309 __IO uint32_t FLTJCHGR;
310 __IO uint32_t FLTFCR;
311 __IO uint32_t FLTJDATAR;
312 __IO uint32_t FLTRDATAR;
313 __IO uint32_t FLTAWHTR;
314 __IO uint32_t FLTAWLTR;
315 __IO uint32_t FLTAWSR;
316 __IO uint32_t FLTAWCFR;
317 __IO uint32_t FLTEXMAX;
318 __IO uint32_t FLTEXMIN;
319 __IO uint32_t FLTCNVTIMR;
320} DFSDM_Filter_TypeDef;
321
325typedef struct
326{
327 __IO uint32_t CHCFGR1;
328 __IO uint32_t CHCFGR2;
329 __IO uint32_t CHAWSCDR;
331 __IO uint32_t CHWDATAR;
332 __IO uint32_t CHDATINR;
333} DFSDM_Channel_TypeDef;
334
338
339typedef struct
340{
341 __IO uint32_t CR;
342 __IO uint32_t SWTRIGR;
343 __IO uint32_t DHR12R1;
344 __IO uint32_t DHR12L1;
345 __IO uint32_t DHR8R1;
346 __IO uint32_t DHR12R2;
347 __IO uint32_t DHR12L2;
348 __IO uint32_t DHR8R2;
349 __IO uint32_t DHR12RD;
350 __IO uint32_t DHR12LD;
351 __IO uint32_t DHR8RD;
352 __IO uint32_t DOR1;
353 __IO uint32_t DOR2;
354 __IO uint32_t SR;
355} DAC_TypeDef;
356
360
361typedef struct
362{
363 __IO uint32_t IDCODE;
364 __IO uint32_t CR;
365 __IO uint32_t APB1FZ;
366 __IO uint32_t APB2FZ;
367} DBGMCU_TypeDef;
368
369
373
374typedef struct
375{
376 __IO uint32_t CR;
377 __IO uint32_t NDTR;
378 __IO uint32_t PAR;
379 __IO uint32_t M0AR;
380 __IO uint32_t M1AR;
381 __IO uint32_t FCR;
382} DMA_Stream_TypeDef;
383
384typedef struct
385{
386 __IO uint32_t LISR;
387 __IO uint32_t HISR;
388 __IO uint32_t LIFCR;
389 __IO uint32_t HIFCR;
390} DMA_TypeDef;
391
395
396typedef struct
397{
398 __IO uint32_t IMR;
399 __IO uint32_t EMR;
400 __IO uint32_t RTSR;
401 __IO uint32_t FTSR;
402 __IO uint32_t SWIER;
403 __IO uint32_t PR;
404} EXTI_TypeDef;
405
409
410typedef struct
411{
412 __IO uint32_t ACR;
413 __IO uint32_t KEYR;
414 __IO uint32_t OPTKEYR;
415 __IO uint32_t SR;
416 __IO uint32_t CR;
417 __IO uint32_t OPTCR;
418 __IO uint32_t OPTCR1;
419} FLASH_TypeDef;
420
421
422
426
427typedef struct
428{
429 __IO uint32_t BTCR[8];
430} FSMC_Bank1_TypeDef;
431
435
436typedef struct
437{
438 __IO uint32_t BWTR[7];
439} FSMC_Bank1E_TypeDef;
443
444typedef struct
445{
446 __IO uint32_t MODER;
447 __IO uint32_t OTYPER;
448 __IO uint32_t OSPEEDR;
449 __IO uint32_t PUPDR;
450 __IO uint32_t IDR;
451 __IO uint32_t ODR;
452 __IO uint32_t BSRR;
453 __IO uint32_t LCKR;
454 __IO uint32_t AFR[2];
455} GPIO_TypeDef;
456
460
461typedef struct
462{
463 __IO uint32_t MEMRMP;
464 __IO uint32_t PMC;
465 __IO uint32_t EXTICR[4];
466 uint32_t RESERVED;
467 __IO uint32_t CFGR2;
468 __IO uint32_t CMPCR;
469 uint32_t RESERVED1[2];
470 __IO uint32_t CFGR;
471 __IO uint32_t MCHDLYCR;
472} SYSCFG_TypeDef;
473
477
478typedef struct
479{
480 __IO uint32_t CR1;
481 __IO uint32_t CR2;
482 __IO uint32_t OAR1;
483 __IO uint32_t OAR2;
484 __IO uint32_t DR;
485 __IO uint32_t SR1;
486 __IO uint32_t SR2;
487 __IO uint32_t CCR;
488 __IO uint32_t TRISE;
489 __IO uint32_t FLTR;
490} I2C_TypeDef;
491
495
496typedef struct
497{
498 __IO uint32_t CR1;
499 __IO uint32_t CR2;
500 __IO uint32_t OAR1;
501 __IO uint32_t OAR2;
502 __IO uint32_t TIMINGR;
503 __IO uint32_t TIMEOUTR;
504 __IO uint32_t ISR;
505 __IO uint32_t ICR;
506 __IO uint32_t PECR;
507 __IO uint32_t RXDR;
508 __IO uint32_t TXDR;
509} FMPI2C_TypeDef;
510
514
515typedef struct
516{
517 __IO uint32_t KR;
518 __IO uint32_t PR;
519 __IO uint32_t RLR;
520 __IO uint32_t SR;
521} IWDG_TypeDef;
522
523
527
528typedef struct
529{
530 __IO uint32_t CR;
531 __IO uint32_t CSR;
532} PWR_TypeDef;
533
537
538typedef struct
539{
540 __IO uint32_t CR;
541 __IO uint32_t PLLCFGR;
542 __IO uint32_t CFGR;
543 __IO uint32_t CIR;
544 __IO uint32_t AHB1RSTR;
545 __IO uint32_t AHB2RSTR;
546 __IO uint32_t AHB3RSTR;
547 uint32_t RESERVED0;
548 __IO uint32_t APB1RSTR;
549 __IO uint32_t APB2RSTR;
550 uint32_t RESERVED1[2];
551 __IO uint32_t AHB1ENR;
552 __IO uint32_t AHB2ENR;
553 __IO uint32_t AHB3ENR;
554 uint32_t RESERVED2;
555 __IO uint32_t APB1ENR;
556 __IO uint32_t APB2ENR;
557 uint32_t RESERVED3[2];
558 __IO uint32_t AHB1LPENR;
559 __IO uint32_t AHB2LPENR;
560 __IO uint32_t AHB3LPENR;
561 uint32_t RESERVED4;
562 __IO uint32_t APB1LPENR;
563 __IO uint32_t APB2LPENR;
564 uint32_t RESERVED5[2];
565 __IO uint32_t BDCR;
566 __IO uint32_t CSR;
567 uint32_t RESERVED6[2];
568 __IO uint32_t SSCGR;
569 __IO uint32_t PLLI2SCFGR;
570 uint32_t RESERVED7;
571 __IO uint32_t DCKCFGR;
572 __IO uint32_t CKGATENR;
573 __IO uint32_t DCKCFGR2;
574} RCC_TypeDef;
575
579
580typedef struct
581{
582 __IO uint32_t TR;
583 __IO uint32_t DR;
584 __IO uint32_t CR;
585 __IO uint32_t ISR;
586 __IO uint32_t PRER;
587 __IO uint32_t WUTR;
588 __IO uint32_t CALIBR;
589 __IO uint32_t ALRMAR;
590 __IO uint32_t ALRMBR;
591 __IO uint32_t WPR;
592 __IO uint32_t SSR;
593 __IO uint32_t SHIFTR;
594 __IO uint32_t TSTR;
595 __IO uint32_t TSDR;
596 __IO uint32_t TSSSR;
597 __IO uint32_t CALR;
598 __IO uint32_t TAFCR;
599 __IO uint32_t ALRMASSR;
600 __IO uint32_t ALRMBSSR;
601 uint32_t RESERVED7;
602 __IO uint32_t BKP0R;
603 __IO uint32_t BKP1R;
604 __IO uint32_t BKP2R;
605 __IO uint32_t BKP3R;
606 __IO uint32_t BKP4R;
607 __IO uint32_t BKP5R;
608 __IO uint32_t BKP6R;
609 __IO uint32_t BKP7R;
610 __IO uint32_t BKP8R;
611 __IO uint32_t BKP9R;
612 __IO uint32_t BKP10R;
613 __IO uint32_t BKP11R;
614 __IO uint32_t BKP12R;
615 __IO uint32_t BKP13R;
616 __IO uint32_t BKP14R;
617 __IO uint32_t BKP15R;
618 __IO uint32_t BKP16R;
619 __IO uint32_t BKP17R;
620 __IO uint32_t BKP18R;
621 __IO uint32_t BKP19R;
622} RTC_TypeDef;
623
627
628typedef struct
629{
630 __IO uint32_t GCR;
631} SAI_TypeDef;
632
633typedef struct
634{
635 __IO uint32_t CR1;
636 __IO uint32_t CR2;
637 __IO uint32_t FRCR;
638 __IO uint32_t SLOTR;
639 __IO uint32_t IMR;
640 __IO uint32_t SR;
641 __IO uint32_t CLRFR;
642 __IO uint32_t DR;
643} SAI_Block_TypeDef;
644
648
649typedef struct
650{
651 __IO uint32_t POWER;
652 __IO uint32_t CLKCR;
653 __IO uint32_t ARG;
654 __IO uint32_t CMD;
655 __IO const uint32_t RESPCMD;
656 __IO const uint32_t RESP1;
657 __IO const uint32_t RESP2;
658 __IO const uint32_t RESP3;
659 __IO const uint32_t RESP4;
660 __IO uint32_t DTIMER;
661 __IO uint32_t DLEN;
662 __IO uint32_t DCTRL;
663 __IO const uint32_t DCOUNT;
664 __IO const uint32_t STA;
665 __IO uint32_t ICR;
666 __IO uint32_t MASK;
667 uint32_t RESERVED0[2];
668 __IO const uint32_t FIFOCNT;
669 uint32_t RESERVED1[13];
670 __IO uint32_t FIFO;
671} SDIO_TypeDef;
672
676
677typedef struct
678{
679 __IO uint32_t CR1;
680 __IO uint32_t CR2;
681 __IO uint32_t SR;
682 __IO uint32_t DR;
683 __IO uint32_t CRCPR;
684 __IO uint32_t RXCRCR;
685 __IO uint32_t TXCRCR;
686 __IO uint32_t I2SCFGR;
687 __IO uint32_t I2SPR;
688} SPI_TypeDef;
689
693
694typedef struct
695{
696 __IO uint32_t CR;
697 __IO uint32_t DCR;
698 __IO uint32_t SR;
699 __IO uint32_t FCR;
700 __IO uint32_t DLR;
701 __IO uint32_t CCR;
702 __IO uint32_t AR;
703 __IO uint32_t ABR;
704 __IO uint32_t DR;
705 __IO uint32_t PSMKR;
706 __IO uint32_t PSMAR;
707 __IO uint32_t PIR;
708 __IO uint32_t LPTR;
709} QUADSPI_TypeDef;
710
714
715typedef struct
716{
717 __IO uint32_t CR1;
718 __IO uint32_t CR2;
719 __IO uint32_t SMCR;
720 __IO uint32_t DIER;
721 __IO uint32_t SR;
722 __IO uint32_t EGR;
723 __IO uint32_t CCMR1;
724 __IO uint32_t CCMR2;
725 __IO uint32_t CCER;
726 __IO uint32_t CNT;
727 __IO uint32_t PSC;
728 __IO uint32_t ARR;
729 __IO uint32_t RCR;
730 __IO uint32_t CCR1;
731 __IO uint32_t CCR2;
732 __IO uint32_t CCR3;
733 __IO uint32_t CCR4;
734 __IO uint32_t BDTR;
735 __IO uint32_t DCR;
736 __IO uint32_t DMAR;
737 __IO uint32_t OR;
738} TIM_TypeDef;
739
743
744typedef struct
745{
746 __IO uint32_t SR;
747 __IO uint32_t DR;
748 __IO uint32_t BRR;
749 __IO uint32_t CR1;
750 __IO uint32_t CR2;
751 __IO uint32_t CR3;
752 __IO uint32_t GTPR;
753} USART_TypeDef;
754
758
759typedef struct
760{
761 __IO uint32_t CR;
762 __IO uint32_t CFR;
763 __IO uint32_t SR;
764} WWDG_TypeDef;
765
769
770typedef struct
771{
772 __IO uint32_t CR;
773 __IO uint32_t SR;
774 __IO uint32_t DINR;
775 __IO uint32_t DOUTR;
776 __IO uint32_t KEYR0;
777 __IO uint32_t KEYR1;
778 __IO uint32_t KEYR2;
779 __IO uint32_t KEYR3;
780 __IO uint32_t IVR0;
781 __IO uint32_t IVR1;
782 __IO uint32_t IVR2;
783 __IO uint32_t IVR3;
784 __IO uint32_t KEYR4;
785 __IO uint32_t KEYR5;
786 __IO uint32_t KEYR6;
787 __IO uint32_t KEYR7;
788 __IO uint32_t SUSP0R;
789 __IO uint32_t SUSP1R;
790 __IO uint32_t SUSP2R;
791 __IO uint32_t SUSP3R;
792 __IO uint32_t SUSP4R;
793 __IO uint32_t SUSP5R;
794 __IO uint32_t SUSP6R;
795 __IO uint32_t SUSP7R;
796} AES_TypeDef;
797
798
802
803typedef struct
804{
805 __IO uint32_t CR;
806 __IO uint32_t SR;
807 __IO uint32_t DR;
808} RNG_TypeDef;
809
813typedef struct
814{
815 __IO uint32_t GOTGCTL;
816 __IO uint32_t GOTGINT;
817 __IO uint32_t GAHBCFG;
818 __IO uint32_t GUSBCFG;
819 __IO uint32_t GRSTCTL;
820 __IO uint32_t GINTSTS;
821 __IO uint32_t GINTMSK;
822 __IO uint32_t GRXSTSR;
823 __IO uint32_t GRXSTSP;
824 __IO uint32_t GRXFSIZ;
825 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
826 __IO uint32_t HNPTXSTS;
827 uint32_t Reserved30[2];
828 __IO uint32_t GCCFG;
829 __IO uint32_t CID;
830 uint32_t Reserved5[3];
831 __IO uint32_t GHWCFG3;
832 uint32_t Reserved6;
833 __IO uint32_t GLPMCFG;
834 uint32_t Reserved;
835 __IO uint32_t GDFIFOCFG;
836 uint32_t Reserved43[40];
837 __IO uint32_t HPTXFSIZ;
838 __IO uint32_t DIEPTXF[0x0F];
839} USB_OTG_GlobalTypeDef;
840
844typedef struct
845{
846 __IO uint32_t DCFG;
847 __IO uint32_t DCTL;
848 __IO uint32_t DSTS;
849 uint32_t Reserved0C;
850 __IO uint32_t DIEPMSK;
851 __IO uint32_t DOEPMSK;
852 __IO uint32_t DAINT;
853 __IO uint32_t DAINTMSK;
854 uint32_t Reserved20;
855 uint32_t Reserved9;
856 __IO uint32_t DVBUSDIS;
857 __IO uint32_t DVBUSPULSE;
858 __IO uint32_t DTHRCTL;
859 __IO uint32_t DIEPEMPMSK;
860 __IO uint32_t DEACHINT;
861 __IO uint32_t DEACHMSK;
862 uint32_t Reserved40;
863 __IO uint32_t DINEP1MSK;
864 uint32_t Reserved44[15];
865 __IO uint32_t DOUTEP1MSK;
866} USB_OTG_DeviceTypeDef;
867
871typedef struct
872{
873 __IO uint32_t DIEPCTL;
874 uint32_t Reserved04;
875 __IO uint32_t DIEPINT;
876 uint32_t Reserved0C;
877 __IO uint32_t DIEPTSIZ;
878 __IO uint32_t DIEPDMA;
879 __IO uint32_t DTXFSTS;
880 uint32_t Reserved18;
881} USB_OTG_INEndpointTypeDef;
882
886typedef struct
887{
888 __IO uint32_t DOEPCTL;
889 uint32_t Reserved04;
890 __IO uint32_t DOEPINT;
891 uint32_t Reserved0C;
892 __IO uint32_t DOEPTSIZ;
893 __IO uint32_t DOEPDMA;
894 uint32_t Reserved18[2];
895} USB_OTG_OUTEndpointTypeDef;
896
900typedef struct
901{
902 __IO uint32_t HCFG;
903 __IO uint32_t HFIR;
904 __IO uint32_t HFNUM;
905 uint32_t Reserved40C;
906 __IO uint32_t HPTXSTS;
907 __IO uint32_t HAINT;
908 __IO uint32_t HAINTMSK;
909} USB_OTG_HostTypeDef;
910
914typedef struct
915{
916 __IO uint32_t HCCHAR;
917 __IO uint32_t HCSPLT;
918 __IO uint32_t HCINT;
919 __IO uint32_t HCINTMSK;
920 __IO uint32_t HCTSIZ;
921 __IO uint32_t HCDMA;
922 uint32_t Reserved[2];
923} USB_OTG_HostChannelTypeDef;
924
928typedef struct
929{
930 __IO uint32_t ISR;
931 __IO uint32_t ICR;
932 __IO uint32_t IER;
933 __IO uint32_t CFGR;
934 __IO uint32_t CR;
935 __IO uint32_t CMP;
936 __IO uint32_t ARR;
937 __IO uint32_t CNT;
938 __IO uint32_t OR;
939} LPTIM_TypeDef;
940
944
948#define FLASH_BASE 0x08000000UL
949#define SRAM1_BASE 0x20000000UL
950#define SRAM2_BASE 0x20040000UL
951#define PERIPH_BASE 0x40000000UL
952#define FSMC_R_BASE 0xA0000000UL
953#define QSPI_R_BASE 0xA0001000UL
954#define SRAM1_BB_BASE 0x22000000UL
955#define SRAM2_BB_BASE 0x22800000UL
956#define PERIPH_BB_BASE 0x42000000UL
957#define FLASH_END 0x0817FFFFUL
958#define FLASH_OTP_BASE 0x1FFF7800UL
959#define FLASH_OTP_END 0x1FFF7A0FUL
960
961/* Legacy defines */
962#define SRAM_BASE SRAM1_BASE
963#define SRAM_BB_BASE SRAM1_BB_BASE
964
966#define APB1PERIPH_BASE PERIPH_BASE
967#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
968#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
969#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
970
972#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
973#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
974#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
975#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
976#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
977#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
978#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
979#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
980#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
981#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL)
982#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
983#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
984#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
985#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
986#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
987#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
988#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
989#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
990#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
991#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
992#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
993#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
994#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
995#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
996#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000UL)
997#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
998#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
999#define CAN3_BASE (APB1PERIPH_BASE + 0x6C00UL)
1000#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
1001#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
1002#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
1003#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
1004
1006#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
1007#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
1008#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
1009#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
1010#define UART9_BASE (APB2PERIPH_BASE + 0x1800UL)
1011#define UART10_BASE (APB2PERIPH_BASE + 0x1C00UL)
1012#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
1013#define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
1014/* Legacy define */
1015#define ADC_BASE ADC1_COMMON_BASE
1016#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
1017#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
1018#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
1019#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
1020#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
1021#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
1022#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
1023#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
1024#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
1025#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL)
1026#define DFSDM2_BASE (APB2PERIPH_BASE + 0x6400UL)
1027#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
1028#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
1029#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
1030#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
1031#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
1032#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
1033#define DFSDM2_Channel0_BASE (DFSDM2_BASE + 0x00UL)
1034#define DFSDM2_Channel1_BASE (DFSDM2_BASE + 0x20UL)
1035#define DFSDM2_Channel2_BASE (DFSDM2_BASE + 0x40UL)
1036#define DFSDM2_Channel3_BASE (DFSDM2_BASE + 0x60UL)
1037#define DFSDM2_Channel4_BASE (DFSDM2_BASE + 0x80UL)
1038#define DFSDM2_Channel5_BASE (DFSDM2_BASE + 0xA0UL)
1039#define DFSDM2_Channel6_BASE (DFSDM2_BASE + 0xC0UL)
1040#define DFSDM2_Channel7_BASE (DFSDM2_BASE + 0xE0UL)
1041#define DFSDM2_Filter0_BASE (DFSDM2_BASE + 0x100UL)
1042#define DFSDM2_Filter1_BASE (DFSDM2_BASE + 0x180UL)
1043#define DFSDM2_Filter2_BASE (DFSDM2_BASE + 0x200UL)
1044#define DFSDM2_Filter3_BASE (DFSDM2_BASE + 0x280UL)
1045#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
1046#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
1047#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
1048
1050#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
1051#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
1052#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
1053#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
1054#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
1055#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
1056#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
1057#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
1058#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1059#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
1060#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
1061#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
1062#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
1063#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
1064#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
1065#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
1066#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
1067#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
1068#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
1069#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
1070#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
1071#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
1072#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
1073#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
1074#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
1075#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
1076#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
1077#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
1078#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
1079
1081#define AES_BASE (AHB2PERIPH_BASE + 0x60000UL)
1082#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
1083
1084
1086#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000UL)
1087#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104UL)
1088
1090#define DBGMCU_BASE 0xE0042000UL
1092#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
1093
1094#define USB_OTG_GLOBAL_BASE 0x000UL
1095#define USB_OTG_DEVICE_BASE 0x800UL
1096#define USB_OTG_IN_ENDPOINT_BASE 0x900UL
1097#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
1098#define USB_OTG_EP_REG_SIZE 0x20UL
1099#define USB_OTG_HOST_BASE 0x400UL
1100#define USB_OTG_HOST_PORT_BASE 0x440UL
1101#define USB_OTG_HOST_CHANNEL_BASE 0x500UL
1102#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
1103#define USB_OTG_PCGCCTL_BASE 0xE00UL
1104#define USB_OTG_FIFO_BASE 0x1000UL
1105#define USB_OTG_FIFO_SIZE 0x1000UL
1106
1107#define UID_BASE 0x1FFF7A10UL
1108#define FLASHSIZE_BASE 0x1FFF7A22UL
1109#define PACKAGE_BASE 0x1FFF7BF0UL
1113
1117#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1118#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1119#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1120#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1121#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1122#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1123#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1124#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1125#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1126#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1127#define RTC ((RTC_TypeDef *) RTC_BASE)
1128#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1129#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1130#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1131#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1132#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1133#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1134#define USART2 ((USART_TypeDef *) USART2_BASE)
1135#define USART3 ((USART_TypeDef *) USART3_BASE)
1136#define UART4 ((USART_TypeDef *) UART4_BASE)
1137#define UART5 ((USART_TypeDef *) UART5_BASE)
1138#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1139#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1140#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1141#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
1142#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1143#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1144#define CAN3 ((CAN_TypeDef *) CAN3_BASE)
1145#define PWR ((PWR_TypeDef *) PWR_BASE)
1146#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1147#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1148#define UART7 ((USART_TypeDef *) UART7_BASE)
1149#define UART8 ((USART_TypeDef *) UART8_BASE)
1150#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1151#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1152#define USART1 ((USART_TypeDef *) USART1_BASE)
1153#define USART6 ((USART_TypeDef *) USART6_BASE)
1154#define UART9 ((USART_TypeDef *) UART9_BASE)
1155#define UART10 ((USART_TypeDef *) UART10_BASE)
1156#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1157#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
1158/* Legacy define */
1159#define ADC ADC1_COMMON
1160#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1161#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1162#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1163#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1164#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1165#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1166#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1167#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1168#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1169#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1170#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1171#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1172#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1173#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1174#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1175#define DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
1176#define DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
1177#define DFSDM2_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel2_BASE)
1178#define DFSDM2_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel3_BASE)
1179#define DFSDM2_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel4_BASE)
1180#define DFSDM2_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel5_BASE)
1181#define DFSDM2_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel6_BASE)
1182#define DFSDM2_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel7_BASE)
1183#define DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter0_BASE)
1184#define DFSDM2_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter1_BASE)
1185#define DFSDM2_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter2_BASE)
1186#define DFSDM2_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter3_BASE)
1187#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1188#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1189#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1190#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1191#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1192#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1193#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1194#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1195#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1196#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1197#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1198#define CRC ((CRC_TypeDef *) CRC_BASE)
1199#define RCC ((RCC_TypeDef *) RCC_BASE)
1200#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1201#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1202#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1203#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1204#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1205#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1206#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1207#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1208#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1209#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1210#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1211#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1212#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1213#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1214#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1215#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1216#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1217#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1218#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1219#define AES ((AES_TypeDef *) AES_BASE)
1220#define RNG ((RNG_TypeDef *) RNG_BASE)
1221#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1222#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1223#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1224#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1225#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1226
1230
1234
1238#define LSI_STARTUP_TIME 40U
1242
1246
1247/******************************************************************************/
1248/* Peripheral Registers_Bits_Definition */
1249/******************************************************************************/
1250
1251/******************************************************************************/
1252/* */
1253/* Analog to Digital Converter */
1254/* */
1255/******************************************************************************/
1256
1257/******************** Bit definition for ADC_SR register ********************/
1258#define ADC_SR_AWD_Pos (0U)
1259#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1260#define ADC_SR_AWD ADC_SR_AWD_Msk
1261#define ADC_SR_EOC_Pos (1U)
1262#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1263#define ADC_SR_EOC ADC_SR_EOC_Msk
1264#define ADC_SR_JEOC_Pos (2U)
1265#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1266#define ADC_SR_JEOC ADC_SR_JEOC_Msk
1267#define ADC_SR_JSTRT_Pos (3U)
1268#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1269#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1270#define ADC_SR_STRT_Pos (4U)
1271#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1272#define ADC_SR_STRT ADC_SR_STRT_Msk
1273#define ADC_SR_OVR_Pos (5U)
1274#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1275#define ADC_SR_OVR ADC_SR_OVR_Msk
1276
1277/******************* Bit definition for ADC_CR1 register ********************/
1278#define ADC_CR1_AWDCH_Pos (0U)
1279#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1280#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1281#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1282#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1283#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1284#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1285#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1286#define ADC_CR1_EOCIE_Pos (5U)
1287#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1288#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1289#define ADC_CR1_AWDIE_Pos (6U)
1290#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1291#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1292#define ADC_CR1_JEOCIE_Pos (7U)
1293#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1294#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1295#define ADC_CR1_SCAN_Pos (8U)
1296#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1297#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1298#define ADC_CR1_AWDSGL_Pos (9U)
1299#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1300#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1301#define ADC_CR1_JAUTO_Pos (10U)
1302#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1303#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1304#define ADC_CR1_DISCEN_Pos (11U)
1305#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1306#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1307#define ADC_CR1_JDISCEN_Pos (12U)
1308#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1309#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1310#define ADC_CR1_DISCNUM_Pos (13U)
1311#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1312#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1313#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1314#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1315#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1316#define ADC_CR1_JAWDEN_Pos (22U)
1317#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1318#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1319#define ADC_CR1_AWDEN_Pos (23U)
1320#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1321#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1322#define ADC_CR1_RES_Pos (24U)
1323#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1324#define ADC_CR1_RES ADC_CR1_RES_Msk
1325#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1326#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1327#define ADC_CR1_OVRIE_Pos (26U)
1328#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1329#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1330
1331/******************* Bit definition for ADC_CR2 register ********************/
1332#define ADC_CR2_ADON_Pos (0U)
1333#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1334#define ADC_CR2_ADON ADC_CR2_ADON_Msk
1335#define ADC_CR2_CONT_Pos (1U)
1336#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1337#define ADC_CR2_CONT ADC_CR2_CONT_Msk
1338#define ADC_CR2_DMA_Pos (8U)
1339#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1340#define ADC_CR2_DMA ADC_CR2_DMA_Msk
1341#define ADC_CR2_DDS_Pos (9U)
1342#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1343#define ADC_CR2_DDS ADC_CR2_DDS_Msk
1344#define ADC_CR2_EOCS_Pos (10U)
1345#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1346#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1347#define ADC_CR2_ALIGN_Pos (11U)
1348#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1349#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1350#define ADC_CR2_JEXTSEL_Pos (16U)
1351#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1352#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1353#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1354#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1355#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1356#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1357#define ADC_CR2_JEXTEN_Pos (20U)
1358#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1359#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1360#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1361#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1362#define ADC_CR2_JSWSTART_Pos (22U)
1363#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1364#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1365#define ADC_CR2_EXTSEL_Pos (24U)
1366#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1367#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1368#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1369#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1370#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1371#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1372#define ADC_CR2_EXTEN_Pos (28U)
1373#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1374#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1375#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1376#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1377#define ADC_CR2_SWSTART_Pos (30U)
1378#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1379#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1380
1381/****************** Bit definition for ADC_SMPR1 register *******************/
1382#define ADC_SMPR1_SMP10_Pos (0U)
1383#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1384#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1385#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1386#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1387#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1388#define ADC_SMPR1_SMP11_Pos (3U)
1389#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1390#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1391#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1392#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1393#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1394#define ADC_SMPR1_SMP12_Pos (6U)
1395#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1396#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1397#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1398#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1399#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1400#define ADC_SMPR1_SMP13_Pos (9U)
1401#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1402#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1403#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1404#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1405#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1406#define ADC_SMPR1_SMP14_Pos (12U)
1407#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1408#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1409#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1410#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1411#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1412#define ADC_SMPR1_SMP15_Pos (15U)
1413#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1414#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1415#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1416#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1417#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1418#define ADC_SMPR1_SMP16_Pos (18U)
1419#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1420#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1421#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1422#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1423#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1424#define ADC_SMPR1_SMP17_Pos (21U)
1425#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1426#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1427#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1428#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1429#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1430#define ADC_SMPR1_SMP18_Pos (24U)
1431#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1432#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1433#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1434#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1435#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1436
1437/****************** Bit definition for ADC_SMPR2 register *******************/
1438#define ADC_SMPR2_SMP0_Pos (0U)
1439#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1440#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1441#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1442#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1443#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1444#define ADC_SMPR2_SMP1_Pos (3U)
1445#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1446#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1447#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1448#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1449#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1450#define ADC_SMPR2_SMP2_Pos (6U)
1451#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1452#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1453#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1454#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1455#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1456#define ADC_SMPR2_SMP3_Pos (9U)
1457#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1458#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1459#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1460#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1461#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1462#define ADC_SMPR2_SMP4_Pos (12U)
1463#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1464#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1465#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1466#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1467#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1468#define ADC_SMPR2_SMP5_Pos (15U)
1469#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1470#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1471#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1472#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1473#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1474#define ADC_SMPR2_SMP6_Pos (18U)
1475#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1476#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1477#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1478#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1479#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1480#define ADC_SMPR2_SMP7_Pos (21U)
1481#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1482#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1483#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1484#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1485#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1486#define ADC_SMPR2_SMP8_Pos (24U)
1487#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1488#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1489#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1490#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1491#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1492#define ADC_SMPR2_SMP9_Pos (27U)
1493#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1494#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1495#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1496#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1497#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1498
1499/****************** Bit definition for ADC_JOFR1 register *******************/
1500#define ADC_JOFR1_JOFFSET1_Pos (0U)
1501#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1502#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1503
1504/****************** Bit definition for ADC_JOFR2 register *******************/
1505#define ADC_JOFR2_JOFFSET2_Pos (0U)
1506#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1507#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1508
1509/****************** Bit definition for ADC_JOFR3 register *******************/
1510#define ADC_JOFR3_JOFFSET3_Pos (0U)
1511#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1512#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1513
1514/****************** Bit definition for ADC_JOFR4 register *******************/
1515#define ADC_JOFR4_JOFFSET4_Pos (0U)
1516#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1517#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1518
1519/******************* Bit definition for ADC_HTR register ********************/
1520#define ADC_HTR_HT_Pos (0U)
1521#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1522#define ADC_HTR_HT ADC_HTR_HT_Msk
1523
1524/******************* Bit definition for ADC_LTR register ********************/
1525#define ADC_LTR_LT_Pos (0U)
1526#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1527#define ADC_LTR_LT ADC_LTR_LT_Msk
1528
1529/******************* Bit definition for ADC_SQR1 register *******************/
1530#define ADC_SQR1_SQ13_Pos (0U)
1531#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1532#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1533#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1534#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1535#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1536#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1537#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1538#define ADC_SQR1_SQ14_Pos (5U)
1539#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1540#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1541#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1542#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1543#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1544#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1545#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1546#define ADC_SQR1_SQ15_Pos (10U)
1547#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1548#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1549#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1550#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1551#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1552#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1553#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1554#define ADC_SQR1_SQ16_Pos (15U)
1555#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1556#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1557#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1558#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1559#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1560#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1561#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1562#define ADC_SQR1_L_Pos (20U)
1563#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1564#define ADC_SQR1_L ADC_SQR1_L_Msk
1565#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1566#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1567#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1568#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1569
1570/******************* Bit definition for ADC_SQR2 register *******************/
1571#define ADC_SQR2_SQ7_Pos (0U)
1572#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1573#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1574#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1575#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1576#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1577#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1578#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1579#define ADC_SQR2_SQ8_Pos (5U)
1580#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1581#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1582#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1583#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1584#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1585#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1586#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1587#define ADC_SQR2_SQ9_Pos (10U)
1588#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1589#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1590#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1591#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1592#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1593#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1594#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1595#define ADC_SQR2_SQ10_Pos (15U)
1596#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1597#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1598#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1599#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1600#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1601#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1602#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1603#define ADC_SQR2_SQ11_Pos (20U)
1604#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1605#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1606#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1607#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1608#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1609#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1610#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1611#define ADC_SQR2_SQ12_Pos (25U)
1612#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1613#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1614#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1615#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1616#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1617#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1618#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1619
1620/******************* Bit definition for ADC_SQR3 register *******************/
1621#define ADC_SQR3_SQ1_Pos (0U)
1622#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1623#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1624#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1625#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1626#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1627#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1628#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1629#define ADC_SQR3_SQ2_Pos (5U)
1630#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1631#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1632#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1633#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1634#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1635#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1636#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1637#define ADC_SQR3_SQ3_Pos (10U)
1638#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1639#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1640#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1641#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1642#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1643#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1644#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1645#define ADC_SQR3_SQ4_Pos (15U)
1646#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1647#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1648#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1649#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1650#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1651#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1652#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1653#define ADC_SQR3_SQ5_Pos (20U)
1654#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1655#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1656#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1657#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1658#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1659#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1660#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1661#define ADC_SQR3_SQ6_Pos (25U)
1662#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1663#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1664#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1665#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1666#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1667#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1668#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1669
1670/******************* Bit definition for ADC_JSQR register *******************/
1671#define ADC_JSQR_JSQ1_Pos (0U)
1672#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1673#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1674#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1675#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1676#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1677#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1678#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1679#define ADC_JSQR_JSQ2_Pos (5U)
1680#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1681#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1682#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1683#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1684#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1685#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1686#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1687#define ADC_JSQR_JSQ3_Pos (10U)
1688#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1689#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1690#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1691#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1692#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1693#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1694#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1695#define ADC_JSQR_JSQ4_Pos (15U)
1696#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1697#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1698#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1699#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1700#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1701#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1702#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1703#define ADC_JSQR_JL_Pos (20U)
1704#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1705#define ADC_JSQR_JL ADC_JSQR_JL_Msk
1706#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1707#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1708
1709/******************* Bit definition for ADC_JDR1 register *******************/
1710#define ADC_JDR1_JDATA_Pos (0U)
1711#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
1712#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
1713
1714/******************* Bit definition for ADC_JDR2 register *******************/
1715#define ADC_JDR2_JDATA_Pos (0U)
1716#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
1717#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
1718
1719/******************* Bit definition for ADC_JDR3 register *******************/
1720#define ADC_JDR3_JDATA_Pos (0U)
1721#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
1722#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
1723
1724/******************* Bit definition for ADC_JDR4 register *******************/
1725#define ADC_JDR4_JDATA_Pos (0U)
1726#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
1727#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
1728
1729/******************** Bit definition for ADC_DR register ********************/
1730#define ADC_DR_DATA_Pos (0U)
1731#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1732#define ADC_DR_DATA ADC_DR_DATA_Msk
1733#define ADC_DR_ADC2DATA_Pos (16U)
1734#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1735#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1736
1737/******************* Bit definition for ADC_CSR register ********************/
1738#define ADC_CSR_AWD1_Pos (0U)
1739#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1740#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1741#define ADC_CSR_EOC1_Pos (1U)
1742#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1743#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1744#define ADC_CSR_JEOC1_Pos (2U)
1745#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1746#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1747#define ADC_CSR_JSTRT1_Pos (3U)
1748#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1749#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1750#define ADC_CSR_STRT1_Pos (4U)
1751#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1752#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1753#define ADC_CSR_OVR1_Pos (5U)
1754#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1755#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1756
1757/* Legacy defines */
1758#define ADC_CSR_DOVR1 ADC_CSR_OVR1
1759
1760/******************* Bit definition for ADC_CCR register ********************/
1761#define ADC_CCR_MULTI_Pos (0U)
1762#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
1763#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
1764#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
1765#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
1766#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
1767#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
1768#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
1769#define ADC_CCR_DELAY_Pos (8U)
1770#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
1771#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
1772#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
1773#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
1774#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
1775#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
1776#define ADC_CCR_DDS_Pos (13U)
1777#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
1778#define ADC_CCR_DDS ADC_CCR_DDS_Msk
1779#define ADC_CCR_DMA_Pos (14U)
1780#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
1781#define ADC_CCR_DMA ADC_CCR_DMA_Msk
1782#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
1783#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
1784#define ADC_CCR_ADCPRE_Pos (16U)
1785#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
1786#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
1787#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
1788#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
1789#define ADC_CCR_VBATE_Pos (22U)
1790#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
1791#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
1792#define ADC_CCR_TSVREFE_Pos (23U)
1793#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
1794#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
1795
1796/******************* Bit definition for ADC_CDR register ********************/
1797#define ADC_CDR_DATA1_Pos (0U)
1798#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
1799#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
1800#define ADC_CDR_DATA2_Pos (16U)
1801#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
1802#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
1803
1804/* Legacy defines */
1805#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1806#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1807
1808/******************************************************************************/
1809/* */
1810/* Controller Area Network */
1811/* */
1812/******************************************************************************/
1814/******************* Bit definition for CAN_MCR register ********************/
1815#define CAN_MCR_INRQ_Pos (0U)
1816#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
1817#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
1818#define CAN_MCR_SLEEP_Pos (1U)
1819#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
1820#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
1821#define CAN_MCR_TXFP_Pos (2U)
1822#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
1823#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
1824#define CAN_MCR_RFLM_Pos (3U)
1825#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
1826#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
1827#define CAN_MCR_NART_Pos (4U)
1828#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
1829#define CAN_MCR_NART CAN_MCR_NART_Msk
1830#define CAN_MCR_AWUM_Pos (5U)
1831#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
1832#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
1833#define CAN_MCR_ABOM_Pos (6U)
1834#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
1835#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
1836#define CAN_MCR_TTCM_Pos (7U)
1837#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
1838#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
1839#define CAN_MCR_RESET_Pos (15U)
1840#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
1841#define CAN_MCR_RESET CAN_MCR_RESET_Msk
1842#define CAN_MCR_DBF_Pos (16U)
1843#define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
1844#define CAN_MCR_DBF CAN_MCR_DBF_Msk
1845/******************* Bit definition for CAN_MSR register ********************/
1846#define CAN_MSR_INAK_Pos (0U)
1847#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
1848#define CAN_MSR_INAK CAN_MSR_INAK_Msk
1849#define CAN_MSR_SLAK_Pos (1U)
1850#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
1851#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
1852#define CAN_MSR_ERRI_Pos (2U)
1853#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
1854#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
1855#define CAN_MSR_WKUI_Pos (3U)
1856#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
1857#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
1858#define CAN_MSR_SLAKI_Pos (4U)
1859#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
1860#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
1861#define CAN_MSR_TXM_Pos (8U)
1862#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
1863#define CAN_MSR_TXM CAN_MSR_TXM_Msk
1864#define CAN_MSR_RXM_Pos (9U)
1865#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
1866#define CAN_MSR_RXM CAN_MSR_RXM_Msk
1867#define CAN_MSR_SAMP_Pos (10U)
1868#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
1869#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
1870#define CAN_MSR_RX_Pos (11U)
1871#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
1872#define CAN_MSR_RX CAN_MSR_RX_Msk
1873
1874/******************* Bit definition for CAN_TSR register ********************/
1875#define CAN_TSR_RQCP0_Pos (0U)
1876#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
1877#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
1878#define CAN_TSR_TXOK0_Pos (1U)
1879#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
1880#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
1881#define CAN_TSR_ALST0_Pos (2U)
1882#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
1883#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
1884#define CAN_TSR_TERR0_Pos (3U)
1885#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
1886#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
1887#define CAN_TSR_ABRQ0_Pos (7U)
1888#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
1889#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
1890#define CAN_TSR_RQCP1_Pos (8U)
1891#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
1892#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
1893#define CAN_TSR_TXOK1_Pos (9U)
1894#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
1895#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
1896#define CAN_TSR_ALST1_Pos (10U)
1897#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
1898#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
1899#define CAN_TSR_TERR1_Pos (11U)
1900#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
1901#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
1902#define CAN_TSR_ABRQ1_Pos (15U)
1903#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
1904#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
1905#define CAN_TSR_RQCP2_Pos (16U)
1906#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
1907#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
1908#define CAN_TSR_TXOK2_Pos (17U)
1909#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
1910#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
1911#define CAN_TSR_ALST2_Pos (18U)
1912#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
1913#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
1914#define CAN_TSR_TERR2_Pos (19U)
1915#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
1916#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
1917#define CAN_TSR_ABRQ2_Pos (23U)
1918#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
1919#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
1920#define CAN_TSR_CODE_Pos (24U)
1921#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
1922#define CAN_TSR_CODE CAN_TSR_CODE_Msk
1923
1924#define CAN_TSR_TME_Pos (26U)
1925#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
1926#define CAN_TSR_TME CAN_TSR_TME_Msk
1927#define CAN_TSR_TME0_Pos (26U)
1928#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
1929#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
1930#define CAN_TSR_TME1_Pos (27U)
1931#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
1932#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
1933#define CAN_TSR_TME2_Pos (28U)
1934#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
1935#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
1936
1937#define CAN_TSR_LOW_Pos (29U)
1938#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
1939#define CAN_TSR_LOW CAN_TSR_LOW_Msk
1940#define CAN_TSR_LOW0_Pos (29U)
1941#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
1942#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
1943#define CAN_TSR_LOW1_Pos (30U)
1944#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
1945#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
1946#define CAN_TSR_LOW2_Pos (31U)
1947#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
1948#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
1949
1950/******************* Bit definition for CAN_RF0R register *******************/
1951#define CAN_RF0R_FMP0_Pos (0U)
1952#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
1953#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
1954#define CAN_RF0R_FULL0_Pos (3U)
1955#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
1956#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
1957#define CAN_RF0R_FOVR0_Pos (4U)
1958#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
1959#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
1960#define CAN_RF0R_RFOM0_Pos (5U)
1961#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
1962#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
1963
1964/******************* Bit definition for CAN_RF1R register *******************/
1965#define CAN_RF1R_FMP1_Pos (0U)
1966#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
1967#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
1968#define CAN_RF1R_FULL1_Pos (3U)
1969#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
1970#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
1971#define CAN_RF1R_FOVR1_Pos (4U)
1972#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
1973#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
1974#define CAN_RF1R_RFOM1_Pos (5U)
1975#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
1976#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
1977
1978/******************** Bit definition for CAN_IER register *******************/
1979#define CAN_IER_TMEIE_Pos (0U)
1980#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
1981#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
1982#define CAN_IER_FMPIE0_Pos (1U)
1983#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
1984#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
1985#define CAN_IER_FFIE0_Pos (2U)
1986#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
1987#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
1988#define CAN_IER_FOVIE0_Pos (3U)
1989#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
1990#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
1991#define CAN_IER_FMPIE1_Pos (4U)
1992#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
1993#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
1994#define CAN_IER_FFIE1_Pos (5U)
1995#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
1996#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
1997#define CAN_IER_FOVIE1_Pos (6U)
1998#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
1999#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
2000#define CAN_IER_EWGIE_Pos (8U)
2001#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
2002#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
2003#define CAN_IER_EPVIE_Pos (9U)
2004#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
2005#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
2006#define CAN_IER_BOFIE_Pos (10U)
2007#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
2008#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
2009#define CAN_IER_LECIE_Pos (11U)
2010#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
2011#define CAN_IER_LECIE CAN_IER_LECIE_Msk
2012#define CAN_IER_ERRIE_Pos (15U)
2013#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
2014#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
2015#define CAN_IER_WKUIE_Pos (16U)
2016#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
2017#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
2018#define CAN_IER_SLKIE_Pos (17U)
2019#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
2020#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
2021#define CAN_IER_EWGIE_Pos (8U)
2022
2023/******************** Bit definition for CAN_ESR register *******************/
2024#define CAN_ESR_EWGF_Pos (0U)
2025#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
2026#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
2027#define CAN_ESR_EPVF_Pos (1U)
2028#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
2029#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
2030#define CAN_ESR_BOFF_Pos (2U)
2031#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
2032#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
2033
2034#define CAN_ESR_LEC_Pos (4U)
2035#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
2036#define CAN_ESR_LEC CAN_ESR_LEC_Msk
2037#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
2038#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
2039#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
2040
2041#define CAN_ESR_TEC_Pos (16U)
2042#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2043#define CAN_ESR_TEC CAN_ESR_TEC_Msk
2044#define CAN_ESR_REC_Pos (24U)
2045#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2046#define CAN_ESR_REC CAN_ESR_REC_Msk
2047
2048/******************* Bit definition for CAN_BTR register ********************/
2049#define CAN_BTR_BRP_Pos (0U)
2050#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2051#define CAN_BTR_BRP CAN_BTR_BRP_Msk
2052#define CAN_BTR_TS1_Pos (16U)
2053#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2054#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2055#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2056#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2057#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2058#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2059#define CAN_BTR_TS2_Pos (20U)
2060#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2061#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2062#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2063#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2064#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2065#define CAN_BTR_SJW_Pos (24U)
2066#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2067#define CAN_BTR_SJW CAN_BTR_SJW_Msk
2068#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2069#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2070#define CAN_BTR_LBKM_Pos (30U)
2071#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2072#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2073#define CAN_BTR_SILM_Pos (31U)
2074#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2075#define CAN_BTR_SILM CAN_BTR_SILM_Msk
2076
2077
2079/****************** Bit definition for CAN_TI0R register ********************/
2080#define CAN_TI0R_TXRQ_Pos (0U)
2081#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2082#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2083#define CAN_TI0R_RTR_Pos (1U)
2084#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2085#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2086#define CAN_TI0R_IDE_Pos (2U)
2087#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2088#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2089#define CAN_TI0R_EXID_Pos (3U)
2090#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2091#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2092#define CAN_TI0R_STID_Pos (21U)
2093#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2094#define CAN_TI0R_STID CAN_TI0R_STID_Msk
2095
2096/****************** Bit definition for CAN_TDT0R register *******************/
2097#define CAN_TDT0R_DLC_Pos (0U)
2098#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2099#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2100#define CAN_TDT0R_TGT_Pos (8U)
2101#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2102#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2103#define CAN_TDT0R_TIME_Pos (16U)
2104#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2105#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2106
2107/****************** Bit definition for CAN_TDL0R register *******************/
2108#define CAN_TDL0R_DATA0_Pos (0U)
2109#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2110#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2111#define CAN_TDL0R_DATA1_Pos (8U)
2112#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2113#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2114#define CAN_TDL0R_DATA2_Pos (16U)
2115#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2116#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2117#define CAN_TDL0R_DATA3_Pos (24U)
2118#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2119#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2120
2121/****************** Bit definition for CAN_TDH0R register *******************/
2122#define CAN_TDH0R_DATA4_Pos (0U)
2123#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2124#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2125#define CAN_TDH0R_DATA5_Pos (8U)
2126#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2127#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2128#define CAN_TDH0R_DATA6_Pos (16U)
2129#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2130#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2131#define CAN_TDH0R_DATA7_Pos (24U)
2132#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2133#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2134
2135/******************* Bit definition for CAN_TI1R register *******************/
2136#define CAN_TI1R_TXRQ_Pos (0U)
2137#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2138#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2139#define CAN_TI1R_RTR_Pos (1U)
2140#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2141#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2142#define CAN_TI1R_IDE_Pos (2U)
2143#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2144#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2145#define CAN_TI1R_EXID_Pos (3U)
2146#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2147#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2148#define CAN_TI1R_STID_Pos (21U)
2149#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2150#define CAN_TI1R_STID CAN_TI1R_STID_Msk
2151
2152/******************* Bit definition for CAN_TDT1R register ******************/
2153#define CAN_TDT1R_DLC_Pos (0U)
2154#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2155#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2156#define CAN_TDT1R_TGT_Pos (8U)
2157#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2158#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2159#define CAN_TDT1R_TIME_Pos (16U)
2160#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2161#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2162
2163/******************* Bit definition for CAN_TDL1R register ******************/
2164#define CAN_TDL1R_DATA0_Pos (0U)
2165#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2166#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2167#define CAN_TDL1R_DATA1_Pos (8U)
2168#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2169#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2170#define CAN_TDL1R_DATA2_Pos (16U)
2171#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2172#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2173#define CAN_TDL1R_DATA3_Pos (24U)
2174#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2175#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2176
2177/******************* Bit definition for CAN_TDH1R register ******************/
2178#define CAN_TDH1R_DATA4_Pos (0U)
2179#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2180#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2181#define CAN_TDH1R_DATA5_Pos (8U)
2182#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2183#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2184#define CAN_TDH1R_DATA6_Pos (16U)
2185#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2186#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2187#define CAN_TDH1R_DATA7_Pos (24U)
2188#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2189#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2190
2191/******************* Bit definition for CAN_TI2R register *******************/
2192#define CAN_TI2R_TXRQ_Pos (0U)
2193#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2194#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2195#define CAN_TI2R_RTR_Pos (1U)
2196#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2197#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2198#define CAN_TI2R_IDE_Pos (2U)
2199#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2200#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2201#define CAN_TI2R_EXID_Pos (3U)
2202#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2203#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2204#define CAN_TI2R_STID_Pos (21U)
2205#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2206#define CAN_TI2R_STID CAN_TI2R_STID_Msk
2207
2208/******************* Bit definition for CAN_TDT2R register ******************/
2209#define CAN_TDT2R_DLC_Pos (0U)
2210#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2211#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2212#define CAN_TDT2R_TGT_Pos (8U)
2213#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2214#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2215#define CAN_TDT2R_TIME_Pos (16U)
2216#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2217#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2218
2219/******************* Bit definition for CAN_TDL2R register ******************/
2220#define CAN_TDL2R_DATA0_Pos (0U)
2221#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2222#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2223#define CAN_TDL2R_DATA1_Pos (8U)
2224#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2225#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2226#define CAN_TDL2R_DATA2_Pos (16U)
2227#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2228#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2229#define CAN_TDL2R_DATA3_Pos (24U)
2230#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2231#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2232
2233/******************* Bit definition for CAN_TDH2R register ******************/
2234#define CAN_TDH2R_DATA4_Pos (0U)
2235#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2236#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2237#define CAN_TDH2R_DATA5_Pos (8U)
2238#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2239#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2240#define CAN_TDH2R_DATA6_Pos (16U)
2241#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2242#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2243#define CAN_TDH2R_DATA7_Pos (24U)
2244#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2245#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2246
2247/******************* Bit definition for CAN_RI0R register *******************/
2248#define CAN_RI0R_RTR_Pos (1U)
2249#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2250#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2251#define CAN_RI0R_IDE_Pos (2U)
2252#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2253#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2254#define CAN_RI0R_EXID_Pos (3U)
2255#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2256#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2257#define CAN_RI0R_STID_Pos (21U)
2258#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2259#define CAN_RI0R_STID CAN_RI0R_STID_Msk
2260
2261/******************* Bit definition for CAN_RDT0R register ******************/
2262#define CAN_RDT0R_DLC_Pos (0U)
2263#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2264#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2265#define CAN_RDT0R_FMI_Pos (8U)
2266#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2267#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2268#define CAN_RDT0R_TIME_Pos (16U)
2269#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2270#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2271
2272/******************* Bit definition for CAN_RDL0R register ******************/
2273#define CAN_RDL0R_DATA0_Pos (0U)
2274#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2275#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2276#define CAN_RDL0R_DATA1_Pos (8U)
2277#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2278#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2279#define CAN_RDL0R_DATA2_Pos (16U)
2280#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2281#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2282#define CAN_RDL0R_DATA3_Pos (24U)
2283#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2284#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2285
2286/******************* Bit definition for CAN_RDH0R register ******************/
2287#define CAN_RDH0R_DATA4_Pos (0U)
2288#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2289#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2290#define CAN_RDH0R_DATA5_Pos (8U)
2291#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2292#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2293#define CAN_RDH0R_DATA6_Pos (16U)
2294#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2295#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2296#define CAN_RDH0R_DATA7_Pos (24U)
2297#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2298#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2299
2300/******************* Bit definition for CAN_RI1R register *******************/
2301#define CAN_RI1R_RTR_Pos (1U)
2302#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2303#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2304#define CAN_RI1R_IDE_Pos (2U)
2305#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2306#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2307#define CAN_RI1R_EXID_Pos (3U)
2308#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2309#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2310#define CAN_RI1R_STID_Pos (21U)
2311#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2312#define CAN_RI1R_STID CAN_RI1R_STID_Msk
2313
2314/******************* Bit definition for CAN_RDT1R register ******************/
2315#define CAN_RDT1R_DLC_Pos (0U)
2316#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2317#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2318#define CAN_RDT1R_FMI_Pos (8U)
2319#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2320#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2321#define CAN_RDT1R_TIME_Pos (16U)
2322#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2323#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2324
2325/******************* Bit definition for CAN_RDL1R register ******************/
2326#define CAN_RDL1R_DATA0_Pos (0U)
2327#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2328#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2329#define CAN_RDL1R_DATA1_Pos (8U)
2330#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2331#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2332#define CAN_RDL1R_DATA2_Pos (16U)
2333#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2334#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2335#define CAN_RDL1R_DATA3_Pos (24U)
2336#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2337#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2338
2339/******************* Bit definition for CAN_RDH1R register ******************/
2340#define CAN_RDH1R_DATA4_Pos (0U)
2341#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2342#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2343#define CAN_RDH1R_DATA5_Pos (8U)
2344#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2345#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2346#define CAN_RDH1R_DATA6_Pos (16U)
2347#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2348#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2349#define CAN_RDH1R_DATA7_Pos (24U)
2350#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2351#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2352
2354/******************* Bit definition for CAN_FMR register ********************/
2355#define CAN_FMR_FINIT_Pos (0U)
2356#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
2357#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
2358#define CAN_FMR_CAN2SB_Pos (8U)
2359#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
2360#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
2361
2362/******************* Bit definition for CAN_FM1R register *******************/
2363#define CAN_FM1R_FBM_Pos (0U)
2364#define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
2365#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2366#define CAN_FM1R_FBM0_Pos (0U)
2367#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2368#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2369#define CAN_FM1R_FBM1_Pos (1U)
2370#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2371#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2372#define CAN_FM1R_FBM2_Pos (2U)
2373#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2374#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2375#define CAN_FM1R_FBM3_Pos (3U)
2376#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2377#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2378#define CAN_FM1R_FBM4_Pos (4U)
2379#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2380#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2381#define CAN_FM1R_FBM5_Pos (5U)
2382#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2383#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2384#define CAN_FM1R_FBM6_Pos (6U)
2385#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2386#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2387#define CAN_FM1R_FBM7_Pos (7U)
2388#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2389#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2390#define CAN_FM1R_FBM8_Pos (8U)
2391#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2392#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2393#define CAN_FM1R_FBM9_Pos (9U)
2394#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2395#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2396#define CAN_FM1R_FBM10_Pos (10U)
2397#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2398#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2399#define CAN_FM1R_FBM11_Pos (11U)
2400#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2401#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2402#define CAN_FM1R_FBM12_Pos (12U)
2403#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2404#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2405#define CAN_FM1R_FBM13_Pos (13U)
2406#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2407#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2408#define CAN_FM1R_FBM14_Pos (14U)
2409#define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)
2410#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk
2411#define CAN_FM1R_FBM15_Pos (15U)
2412#define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)
2413#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk
2414#define CAN_FM1R_FBM16_Pos (16U)
2415#define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)
2416#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk
2417#define CAN_FM1R_FBM17_Pos (17U)
2418#define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)
2419#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk
2420#define CAN_FM1R_FBM18_Pos (18U)
2421#define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)
2422#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk
2423#define CAN_FM1R_FBM19_Pos (19U)
2424#define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)
2425#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk
2426#define CAN_FM1R_FBM20_Pos (20U)
2427#define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)
2428#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk
2429#define CAN_FM1R_FBM21_Pos (21U)
2430#define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)
2431#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk
2432#define CAN_FM1R_FBM22_Pos (22U)
2433#define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)
2434#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk
2435#define CAN_FM1R_FBM23_Pos (23U)
2436#define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)
2437#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk
2438#define CAN_FM1R_FBM24_Pos (24U)
2439#define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)
2440#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk
2441#define CAN_FM1R_FBM25_Pos (25U)
2442#define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)
2443#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk
2444#define CAN_FM1R_FBM26_Pos (26U)
2445#define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)
2446#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk
2447#define CAN_FM1R_FBM27_Pos (27U)
2448#define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)
2449#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk
2450
2451/******************* Bit definition for CAN_FS1R register *******************/
2452#define CAN_FS1R_FSC_Pos (0U)
2453#define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
2454#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2455#define CAN_FS1R_FSC0_Pos (0U)
2456#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2457#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2458#define CAN_FS1R_FSC1_Pos (1U)
2459#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2460#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2461#define CAN_FS1R_FSC2_Pos (2U)
2462#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2463#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2464#define CAN_FS1R_FSC3_Pos (3U)
2465#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2466#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2467#define CAN_FS1R_FSC4_Pos (4U)
2468#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2469#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2470#define CAN_FS1R_FSC5_Pos (5U)
2471#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2472#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2473#define CAN_FS1R_FSC6_Pos (6U)
2474#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2475#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2476#define CAN_FS1R_FSC7_Pos (7U)
2477#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2478#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2479#define CAN_FS1R_FSC8_Pos (8U)
2480#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2481#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2482#define CAN_FS1R_FSC9_Pos (9U)
2483#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2484#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2485#define CAN_FS1R_FSC10_Pos (10U)
2486#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2487#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2488#define CAN_FS1R_FSC11_Pos (11U)
2489#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2490#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2491#define CAN_FS1R_FSC12_Pos (12U)
2492#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2493#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2494#define CAN_FS1R_FSC13_Pos (13U)
2495#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2496#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2497#define CAN_FS1R_FSC14_Pos (14U)
2498#define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)
2499#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk
2500#define CAN_FS1R_FSC15_Pos (15U)
2501#define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)
2502#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk
2503#define CAN_FS1R_FSC16_Pos (16U)
2504#define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)
2505#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk
2506#define CAN_FS1R_FSC17_Pos (17U)
2507#define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)
2508#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk
2509#define CAN_FS1R_FSC18_Pos (18U)
2510#define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)
2511#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk
2512#define CAN_FS1R_FSC19_Pos (19U)
2513#define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)
2514#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk
2515#define CAN_FS1R_FSC20_Pos (20U)
2516#define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)
2517#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk
2518#define CAN_FS1R_FSC21_Pos (21U)
2519#define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)
2520#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk
2521#define CAN_FS1R_FSC22_Pos (22U)
2522#define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)
2523#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk
2524#define CAN_FS1R_FSC23_Pos (23U)
2525#define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)
2526#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk
2527#define CAN_FS1R_FSC24_Pos (24U)
2528#define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)
2529#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk
2530#define CAN_FS1R_FSC25_Pos (25U)
2531#define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)
2532#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk
2533#define CAN_FS1R_FSC26_Pos (26U)
2534#define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)
2535#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk
2536#define CAN_FS1R_FSC27_Pos (27U)
2537#define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)
2538#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk
2539
2540/****************** Bit definition for CAN_FFA1R register *******************/
2541#define CAN_FFA1R_FFA_Pos (0U)
2542#define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
2543#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2544#define CAN_FFA1R_FFA0_Pos (0U)
2545#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2546#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2547#define CAN_FFA1R_FFA1_Pos (1U)
2548#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2549#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2550#define CAN_FFA1R_FFA2_Pos (2U)
2551#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2552#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2553#define CAN_FFA1R_FFA3_Pos (3U)
2554#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2555#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2556#define CAN_FFA1R_FFA4_Pos (4U)
2557#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2558#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2559#define CAN_FFA1R_FFA5_Pos (5U)
2560#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2561#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2562#define CAN_FFA1R_FFA6_Pos (6U)
2563#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2564#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2565#define CAN_FFA1R_FFA7_Pos (7U)
2566#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2567#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2568#define CAN_FFA1R_FFA8_Pos (8U)
2569#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2570#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2571#define CAN_FFA1R_FFA9_Pos (9U)
2572#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2573#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2574#define CAN_FFA1R_FFA10_Pos (10U)
2575#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2576#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2577#define CAN_FFA1R_FFA11_Pos (11U)
2578#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2579#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2580#define CAN_FFA1R_FFA12_Pos (12U)
2581#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2582#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2583#define CAN_FFA1R_FFA13_Pos (13U)
2584#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2585#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2586#define CAN_FFA1R_FFA14_Pos (14U)
2587#define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)
2588#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk
2589#define CAN_FFA1R_FFA15_Pos (15U)
2590#define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)
2591#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk
2592#define CAN_FFA1R_FFA16_Pos (16U)
2593#define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)
2594#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk
2595#define CAN_FFA1R_FFA17_Pos (17U)
2596#define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)
2597#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk
2598#define CAN_FFA1R_FFA18_Pos (18U)
2599#define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)
2600#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk
2601#define CAN_FFA1R_FFA19_Pos (19U)
2602#define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)
2603#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk
2604#define CAN_FFA1R_FFA20_Pos (20U)
2605#define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)
2606#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk
2607#define CAN_FFA1R_FFA21_Pos (21U)
2608#define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)
2609#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk
2610#define CAN_FFA1R_FFA22_Pos (22U)
2611#define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)
2612#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk
2613#define CAN_FFA1R_FFA23_Pos (23U)
2614#define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)
2615#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk
2616#define CAN_FFA1R_FFA24_Pos (24U)
2617#define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)
2618#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk
2619#define CAN_FFA1R_FFA25_Pos (25U)
2620#define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)
2621#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk
2622#define CAN_FFA1R_FFA26_Pos (26U)
2623#define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)
2624#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk
2625#define CAN_FFA1R_FFA27_Pos (27U)
2626#define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)
2627#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk
2628
2629/******************* Bit definition for CAN_FA1R register *******************/
2630#define CAN_FA1R_FACT_Pos (0U)
2631#define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
2632#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2633#define CAN_FA1R_FACT0_Pos (0U)
2634#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2635#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2636#define CAN_FA1R_FACT1_Pos (1U)
2637#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2638#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2639#define CAN_FA1R_FACT2_Pos (2U)
2640#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2641#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2642#define CAN_FA1R_FACT3_Pos (3U)
2643#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2644#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2645#define CAN_FA1R_FACT4_Pos (4U)
2646#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2647#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2648#define CAN_FA1R_FACT5_Pos (5U)
2649#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2650#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2651#define CAN_FA1R_FACT6_Pos (6U)
2652#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2653#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2654#define CAN_FA1R_FACT7_Pos (7U)
2655#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2656#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2657#define CAN_FA1R_FACT8_Pos (8U)
2658#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2659#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2660#define CAN_FA1R_FACT9_Pos (9U)
2661#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2662#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2663#define CAN_FA1R_FACT10_Pos (10U)
2664#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2665#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2666#define CAN_FA1R_FACT11_Pos (11U)
2667#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2668#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2669#define CAN_FA1R_FACT12_Pos (12U)
2670#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2671#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2672#define CAN_FA1R_FACT13_Pos (13U)
2673#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2674#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2675#define CAN_FA1R_FACT14_Pos (14U)
2676#define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)
2677#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk
2678#define CAN_FA1R_FACT15_Pos (15U)
2679#define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)
2680#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk
2681#define CAN_FA1R_FACT16_Pos (16U)
2682#define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)
2683#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk
2684#define CAN_FA1R_FACT17_Pos (17U)
2685#define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)
2686#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk
2687#define CAN_FA1R_FACT18_Pos (18U)
2688#define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)
2689#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk
2690#define CAN_FA1R_FACT19_Pos (19U)
2691#define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)
2692#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk
2693#define CAN_FA1R_FACT20_Pos (20U)
2694#define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)
2695#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk
2696#define CAN_FA1R_FACT21_Pos (21U)
2697#define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)
2698#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk
2699#define CAN_FA1R_FACT22_Pos (22U)
2700#define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)
2701#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk
2702#define CAN_FA1R_FACT23_Pos (23U)
2703#define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)
2704#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk
2705#define CAN_FA1R_FACT24_Pos (24U)
2706#define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)
2707#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk
2708#define CAN_FA1R_FACT25_Pos (25U)
2709#define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)
2710#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk
2711#define CAN_FA1R_FACT26_Pos (26U)
2712#define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)
2713#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk
2714#define CAN_FA1R_FACT27_Pos (27U)
2715#define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)
2716#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk
2717
2718
2719/******************* Bit definition for CAN_F0R1 register *******************/
2720#define CAN_F0R1_FB0_Pos (0U)
2721#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2722#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2723#define CAN_F0R1_FB1_Pos (1U)
2724#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
2725#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
2726#define CAN_F0R1_FB2_Pos (2U)
2727#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
2728#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
2729#define CAN_F0R1_FB3_Pos (3U)
2730#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
2731#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
2732#define CAN_F0R1_FB4_Pos (4U)
2733#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
2734#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
2735#define CAN_F0R1_FB5_Pos (5U)
2736#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
2737#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
2738#define CAN_F0R1_FB6_Pos (6U)
2739#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
2740#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
2741#define CAN_F0R1_FB7_Pos (7U)
2742#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
2743#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
2744#define CAN_F0R1_FB8_Pos (8U)
2745#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
2746#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
2747#define CAN_F0R1_FB9_Pos (9U)
2748#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
2749#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
2750#define CAN_F0R1_FB10_Pos (10U)
2751#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
2752#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
2753#define CAN_F0R1_FB11_Pos (11U)
2754#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
2755#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
2756#define CAN_F0R1_FB12_Pos (12U)
2757#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
2758#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
2759#define CAN_F0R1_FB13_Pos (13U)
2760#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
2761#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
2762#define CAN_F0R1_FB14_Pos (14U)
2763#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
2764#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
2765#define CAN_F0R1_FB15_Pos (15U)
2766#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
2767#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
2768#define CAN_F0R1_FB16_Pos (16U)
2769#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
2770#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
2771#define CAN_F0R1_FB17_Pos (17U)
2772#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
2773#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
2774#define CAN_F0R1_FB18_Pos (18U)
2775#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
2776#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
2777#define CAN_F0R1_FB19_Pos (19U)
2778#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
2779#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
2780#define CAN_F0R1_FB20_Pos (20U)
2781#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
2782#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
2783#define CAN_F0R1_FB21_Pos (21U)
2784#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
2785#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
2786#define CAN_F0R1_FB22_Pos (22U)
2787#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
2788#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
2789#define CAN_F0R1_FB23_Pos (23U)
2790#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
2791#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
2792#define CAN_F0R1_FB24_Pos (24U)
2793#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
2794#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
2795#define CAN_F0R1_FB25_Pos (25U)
2796#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
2797#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
2798#define CAN_F0R1_FB26_Pos (26U)
2799#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
2800#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
2801#define CAN_F0R1_FB27_Pos (27U)
2802#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
2803#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
2804#define CAN_F0R1_FB28_Pos (28U)
2805#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
2806#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
2807#define CAN_F0R1_FB29_Pos (29U)
2808#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
2809#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
2810#define CAN_F0R1_FB30_Pos (30U)
2811#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
2812#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
2813#define CAN_F0R1_FB31_Pos (31U)
2814#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
2815#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
2816
2817/******************* Bit definition for CAN_F1R1 register *******************/
2818#define CAN_F1R1_FB0_Pos (0U)
2819#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
2820#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
2821#define CAN_F1R1_FB1_Pos (1U)
2822#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
2823#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
2824#define CAN_F1R1_FB2_Pos (2U)
2825#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
2826#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
2827#define CAN_F1R1_FB3_Pos (3U)
2828#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
2829#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
2830#define CAN_F1R1_FB4_Pos (4U)
2831#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
2832#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
2833#define CAN_F1R1_FB5_Pos (5U)
2834#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
2835#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
2836#define CAN_F1R1_FB6_Pos (6U)
2837#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
2838#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
2839#define CAN_F1R1_FB7_Pos (7U)
2840#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
2841#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
2842#define CAN_F1R1_FB8_Pos (8U)
2843#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
2844#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
2845#define CAN_F1R1_FB9_Pos (9U)
2846#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
2847#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
2848#define CAN_F1R1_FB10_Pos (10U)
2849#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
2850#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
2851#define CAN_F1R1_FB11_Pos (11U)
2852#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
2853#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
2854#define CAN_F1R1_FB12_Pos (12U)
2855#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
2856#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
2857#define CAN_F1R1_FB13_Pos (13U)
2858#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
2859#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
2860#define CAN_F1R1_FB14_Pos (14U)
2861#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
2862#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
2863#define CAN_F1R1_FB15_Pos (15U)
2864#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
2865#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
2866#define CAN_F1R1_FB16_Pos (16U)
2867#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
2868#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
2869#define CAN_F1R1_FB17_Pos (17U)
2870#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
2871#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
2872#define CAN_F1R1_FB18_Pos (18U)
2873#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
2874#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
2875#define CAN_F1R1_FB19_Pos (19U)
2876#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
2877#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
2878#define CAN_F1R1_FB20_Pos (20U)
2879#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
2880#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
2881#define CAN_F1R1_FB21_Pos (21U)
2882#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
2883#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
2884#define CAN_F1R1_FB22_Pos (22U)
2885#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
2886#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
2887#define CAN_F1R1_FB23_Pos (23U)
2888#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
2889#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
2890#define CAN_F1R1_FB24_Pos (24U)
2891#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
2892#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
2893#define CAN_F1R1_FB25_Pos (25U)
2894#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
2895#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
2896#define CAN_F1R1_FB26_Pos (26U)
2897#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
2898#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
2899#define CAN_F1R1_FB27_Pos (27U)
2900#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
2901#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
2902#define CAN_F1R1_FB28_Pos (28U)
2903#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
2904#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
2905#define CAN_F1R1_FB29_Pos (29U)
2906#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
2907#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
2908#define CAN_F1R1_FB30_Pos (30U)
2909#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
2910#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
2911#define CAN_F1R1_FB31_Pos (31U)
2912#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
2913#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
2914
2915/******************* Bit definition for CAN_F2R1 register *******************/
2916#define CAN_F2R1_FB0_Pos (0U)
2917#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
2918#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
2919#define CAN_F2R1_FB1_Pos (1U)
2920#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
2921#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
2922#define CAN_F2R1_FB2_Pos (2U)
2923#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
2924#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
2925#define CAN_F2R1_FB3_Pos (3U)
2926#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
2927#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
2928#define CAN_F2R1_FB4_Pos (4U)
2929#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
2930#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
2931#define CAN_F2R1_FB5_Pos (5U)
2932#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
2933#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
2934#define CAN_F2R1_FB6_Pos (6U)
2935#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
2936#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
2937#define CAN_F2R1_FB7_Pos (7U)
2938#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
2939#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
2940#define CAN_F2R1_FB8_Pos (8U)
2941#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
2942#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
2943#define CAN_F2R1_FB9_Pos (9U)
2944#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
2945#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
2946#define CAN_F2R1_FB10_Pos (10U)
2947#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
2948#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
2949#define CAN_F2R1_FB11_Pos (11U)
2950#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
2951#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
2952#define CAN_F2R1_FB12_Pos (12U)
2953#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
2954#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
2955#define CAN_F2R1_FB13_Pos (13U)
2956#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
2957#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
2958#define CAN_F2R1_FB14_Pos (14U)
2959#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
2960#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
2961#define CAN_F2R1_FB15_Pos (15U)
2962#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
2963#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
2964#define CAN_F2R1_FB16_Pos (16U)
2965#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
2966#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
2967#define CAN_F2R1_FB17_Pos (17U)
2968#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
2969#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
2970#define CAN_F2R1_FB18_Pos (18U)
2971#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
2972#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
2973#define CAN_F2R1_FB19_Pos (19U)
2974#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
2975#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
2976#define CAN_F2R1_FB20_Pos (20U)
2977#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
2978#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
2979#define CAN_F2R1_FB21_Pos (21U)
2980#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
2981#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
2982#define CAN_F2R1_FB22_Pos (22U)
2983#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
2984#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
2985#define CAN_F2R1_FB23_Pos (23U)
2986#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
2987#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
2988#define CAN_F2R1_FB24_Pos (24U)
2989#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
2990#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
2991#define CAN_F2R1_FB25_Pos (25U)
2992#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
2993#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
2994#define CAN_F2R1_FB26_Pos (26U)
2995#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
2996#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
2997#define CAN_F2R1_FB27_Pos (27U)
2998#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
2999#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
3000#define CAN_F2R1_FB28_Pos (28U)
3001#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
3002#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
3003#define CAN_F2R1_FB29_Pos (29U)
3004#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
3005#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
3006#define CAN_F2R1_FB30_Pos (30U)
3007#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
3008#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
3009#define CAN_F2R1_FB31_Pos (31U)
3010#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
3011#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
3012
3013/******************* Bit definition for CAN_F3R1 register *******************/
3014#define CAN_F3R1_FB0_Pos (0U)
3015#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
3016#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
3017#define CAN_F3R1_FB1_Pos (1U)
3018#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
3019#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
3020#define CAN_F3R1_FB2_Pos (2U)
3021#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
3022#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
3023#define CAN_F3R1_FB3_Pos (3U)
3024#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
3025#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
3026#define CAN_F3R1_FB4_Pos (4U)
3027#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
3028#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
3029#define CAN_F3R1_FB5_Pos (5U)
3030#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
3031#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
3032#define CAN_F3R1_FB6_Pos (6U)
3033#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
3034#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
3035#define CAN_F3R1_FB7_Pos (7U)
3036#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
3037#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
3038#define CAN_F3R1_FB8_Pos (8U)
3039#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
3040#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
3041#define CAN_F3R1_FB9_Pos (9U)
3042#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3043#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3044#define CAN_F3R1_FB10_Pos (10U)
3045#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3046#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3047#define CAN_F3R1_FB11_Pos (11U)
3048#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3049#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3050#define CAN_F3R1_FB12_Pos (12U)
3051#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3052#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3053#define CAN_F3R1_FB13_Pos (13U)
3054#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3055#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3056#define CAN_F3R1_FB14_Pos (14U)
3057#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3058#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3059#define CAN_F3R1_FB15_Pos (15U)
3060#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3061#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3062#define CAN_F3R1_FB16_Pos (16U)
3063#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3064#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3065#define CAN_F3R1_FB17_Pos (17U)
3066#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3067#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3068#define CAN_F3R1_FB18_Pos (18U)
3069#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3070#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3071#define CAN_F3R1_FB19_Pos (19U)
3072#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3073#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3074#define CAN_F3R1_FB20_Pos (20U)
3075#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3076#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3077#define CAN_F3R1_FB21_Pos (21U)
3078#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3079#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3080#define CAN_F3R1_FB22_Pos (22U)
3081#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3082#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3083#define CAN_F3R1_FB23_Pos (23U)
3084#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3085#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3086#define CAN_F3R1_FB24_Pos (24U)
3087#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3088#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3089#define CAN_F3R1_FB25_Pos (25U)
3090#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3091#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3092#define CAN_F3R1_FB26_Pos (26U)
3093#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3094#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3095#define CAN_F3R1_FB27_Pos (27U)
3096#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3097#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3098#define CAN_F3R1_FB28_Pos (28U)
3099#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3100#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3101#define CAN_F3R1_FB29_Pos (29U)
3102#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3103#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3104#define CAN_F3R1_FB30_Pos (30U)
3105#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3106#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3107#define CAN_F3R1_FB31_Pos (31U)
3108#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3109#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3110
3111/******************* Bit definition for CAN_F4R1 register *******************/
3112#define CAN_F4R1_FB0_Pos (0U)
3113#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3114#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3115#define CAN_F4R1_FB1_Pos (1U)
3116#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3117#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3118#define CAN_F4R1_FB2_Pos (2U)
3119#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3120#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3121#define CAN_F4R1_FB3_Pos (3U)
3122#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3123#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3124#define CAN_F4R1_FB4_Pos (4U)
3125#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3126#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3127#define CAN_F4R1_FB5_Pos (5U)
3128#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3129#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3130#define CAN_F4R1_FB6_Pos (6U)
3131#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3132#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3133#define CAN_F4R1_FB7_Pos (7U)
3134#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3135#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3136#define CAN_F4R1_FB8_Pos (8U)
3137#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3138#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3139#define CAN_F4R1_FB9_Pos (9U)
3140#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3141#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3142#define CAN_F4R1_FB10_Pos (10U)
3143#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3144#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3145#define CAN_F4R1_FB11_Pos (11U)
3146#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3147#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3148#define CAN_F4R1_FB12_Pos (12U)
3149#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3150#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3151#define CAN_F4R1_FB13_Pos (13U)
3152#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3153#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3154#define CAN_F4R1_FB14_Pos (14U)
3155#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3156#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3157#define CAN_F4R1_FB15_Pos (15U)
3158#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3159#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3160#define CAN_F4R1_FB16_Pos (16U)
3161#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3162#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3163#define CAN_F4R1_FB17_Pos (17U)
3164#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3165#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3166#define CAN_F4R1_FB18_Pos (18U)
3167#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3168#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3169#define CAN_F4R1_FB19_Pos (19U)
3170#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3171#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3172#define CAN_F4R1_FB20_Pos (20U)
3173#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3174#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3175#define CAN_F4R1_FB21_Pos (21U)
3176#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3177#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3178#define CAN_F4R1_FB22_Pos (22U)
3179#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3180#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3181#define CAN_F4R1_FB23_Pos (23U)
3182#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3183#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3184#define CAN_F4R1_FB24_Pos (24U)
3185#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3186#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3187#define CAN_F4R1_FB25_Pos (25U)
3188#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3189#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3190#define CAN_F4R1_FB26_Pos (26U)
3191#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3192#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3193#define CAN_F4R1_FB27_Pos (27U)
3194#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3195#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3196#define CAN_F4R1_FB28_Pos (28U)
3197#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3198#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3199#define CAN_F4R1_FB29_Pos (29U)
3200#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3201#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3202#define CAN_F4R1_FB30_Pos (30U)
3203#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3204#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3205#define CAN_F4R1_FB31_Pos (31U)
3206#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3207#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3208
3209/******************* Bit definition for CAN_F5R1 register *******************/
3210#define CAN_F5R1_FB0_Pos (0U)
3211#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3212#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3213#define CAN_F5R1_FB1_Pos (1U)
3214#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3215#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3216#define CAN_F5R1_FB2_Pos (2U)
3217#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3218#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3219#define CAN_F5R1_FB3_Pos (3U)
3220#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3221#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3222#define CAN_F5R1_FB4_Pos (4U)
3223#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3224#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3225#define CAN_F5R1_FB5_Pos (5U)
3226#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3227#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3228#define CAN_F5R1_FB6_Pos (6U)
3229#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3230#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3231#define CAN_F5R1_FB7_Pos (7U)
3232#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3233#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3234#define CAN_F5R1_FB8_Pos (8U)
3235#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3236#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3237#define CAN_F5R1_FB9_Pos (9U)
3238#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3239#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3240#define CAN_F5R1_FB10_Pos (10U)
3241#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3242#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3243#define CAN_F5R1_FB11_Pos (11U)
3244#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3245#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3246#define CAN_F5R1_FB12_Pos (12U)
3247#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3248#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3249#define CAN_F5R1_FB13_Pos (13U)
3250#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3251#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3252#define CAN_F5R1_FB14_Pos (14U)
3253#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3254#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3255#define CAN_F5R1_FB15_Pos (15U)
3256#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3257#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3258#define CAN_F5R1_FB16_Pos (16U)
3259#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3260#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3261#define CAN_F5R1_FB17_Pos (17U)
3262#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3263#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3264#define CAN_F5R1_FB18_Pos (18U)
3265#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3266#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3267#define CAN_F5R1_FB19_Pos (19U)
3268#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3269#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3270#define CAN_F5R1_FB20_Pos (20U)
3271#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3272#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3273#define CAN_F5R1_FB21_Pos (21U)
3274#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3275#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3276#define CAN_F5R1_FB22_Pos (22U)
3277#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3278#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3279#define CAN_F5R1_FB23_Pos (23U)
3280#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3281#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3282#define CAN_F5R1_FB24_Pos (24U)
3283#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3284#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3285#define CAN_F5R1_FB25_Pos (25U)
3286#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3287#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3288#define CAN_F5R1_FB26_Pos (26U)
3289#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3290#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3291#define CAN_F5R1_FB27_Pos (27U)
3292#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3293#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3294#define CAN_F5R1_FB28_Pos (28U)
3295#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3296#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3297#define CAN_F5R1_FB29_Pos (29U)
3298#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3299#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3300#define CAN_F5R1_FB30_Pos (30U)
3301#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3302#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3303#define CAN_F5R1_FB31_Pos (31U)
3304#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3305#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3306
3307/******************* Bit definition for CAN_F6R1 register *******************/
3308#define CAN_F6R1_FB0_Pos (0U)
3309#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3310#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3311#define CAN_F6R1_FB1_Pos (1U)
3312#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3313#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3314#define CAN_F6R1_FB2_Pos (2U)
3315#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3316#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3317#define CAN_F6R1_FB3_Pos (3U)
3318#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3319#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3320#define CAN_F6R1_FB4_Pos (4U)
3321#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3322#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3323#define CAN_F6R1_FB5_Pos (5U)
3324#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3325#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3326#define CAN_F6R1_FB6_Pos (6U)
3327#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3328#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3329#define CAN_F6R1_FB7_Pos (7U)
3330#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3331#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3332#define CAN_F6R1_FB8_Pos (8U)
3333#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3334#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3335#define CAN_F6R1_FB9_Pos (9U)
3336#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3337#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3338#define CAN_F6R1_FB10_Pos (10U)
3339#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3340#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3341#define CAN_F6R1_FB11_Pos (11U)
3342#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3343#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3344#define CAN_F6R1_FB12_Pos (12U)
3345#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3346#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3347#define CAN_F6R1_FB13_Pos (13U)
3348#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3349#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3350#define CAN_F6R1_FB14_Pos (14U)
3351#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3352#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3353#define CAN_F6R1_FB15_Pos (15U)
3354#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3355#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3356#define CAN_F6R1_FB16_Pos (16U)
3357#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3358#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3359#define CAN_F6R1_FB17_Pos (17U)
3360#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3361#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3362#define CAN_F6R1_FB18_Pos (18U)
3363#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3364#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3365#define CAN_F6R1_FB19_Pos (19U)
3366#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3367#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3368#define CAN_F6R1_FB20_Pos (20U)
3369#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3370#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3371#define CAN_F6R1_FB21_Pos (21U)
3372#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3373#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3374#define CAN_F6R1_FB22_Pos (22U)
3375#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3376#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3377#define CAN_F6R1_FB23_Pos (23U)
3378#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3379#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3380#define CAN_F6R1_FB24_Pos (24U)
3381#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3382#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3383#define CAN_F6R1_FB25_Pos (25U)
3384#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3385#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3386#define CAN_F6R1_FB26_Pos (26U)
3387#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3388#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3389#define CAN_F6R1_FB27_Pos (27U)
3390#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3391#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3392#define CAN_F6R1_FB28_Pos (28U)
3393#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3394#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3395#define CAN_F6R1_FB29_Pos (29U)
3396#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3397#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3398#define CAN_F6R1_FB30_Pos (30U)
3399#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3400#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3401#define CAN_F6R1_FB31_Pos (31U)
3402#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3403#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3404
3405/******************* Bit definition for CAN_F7R1 register *******************/
3406#define CAN_F7R1_FB0_Pos (0U)
3407#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3408#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3409#define CAN_F7R1_FB1_Pos (1U)
3410#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3411#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3412#define CAN_F7R1_FB2_Pos (2U)
3413#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3414#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3415#define CAN_F7R1_FB3_Pos (3U)
3416#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3417#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3418#define CAN_F7R1_FB4_Pos (4U)
3419#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3420#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3421#define CAN_F7R1_FB5_Pos (5U)
3422#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3423#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3424#define CAN_F7R1_FB6_Pos (6U)
3425#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3426#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3427#define CAN_F7R1_FB7_Pos (7U)
3428#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3429#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3430#define CAN_F7R1_FB8_Pos (8U)
3431#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3432#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3433#define CAN_F7R1_FB9_Pos (9U)
3434#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3435#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3436#define CAN_F7R1_FB10_Pos (10U)
3437#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3438#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3439#define CAN_F7R1_FB11_Pos (11U)
3440#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3441#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3442#define CAN_F7R1_FB12_Pos (12U)
3443#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3444#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3445#define CAN_F7R1_FB13_Pos (13U)
3446#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3447#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3448#define CAN_F7R1_FB14_Pos (14U)
3449#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3450#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3451#define CAN_F7R1_FB15_Pos (15U)
3452#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3453#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3454#define CAN_F7R1_FB16_Pos (16U)
3455#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3456#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3457#define CAN_F7R1_FB17_Pos (17U)
3458#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3459#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3460#define CAN_F7R1_FB18_Pos (18U)
3461#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3462#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3463#define CAN_F7R1_FB19_Pos (19U)
3464#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3465#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3466#define CAN_F7R1_FB20_Pos (20U)
3467#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3468#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3469#define CAN_F7R1_FB21_Pos (21U)
3470#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3471#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3472#define CAN_F7R1_FB22_Pos (22U)
3473#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3474#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3475#define CAN_F7R1_FB23_Pos (23U)
3476#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3477#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3478#define CAN_F7R1_FB24_Pos (24U)
3479#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3480#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3481#define CAN_F7R1_FB25_Pos (25U)
3482#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3483#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3484#define CAN_F7R1_FB26_Pos (26U)
3485#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3486#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3487#define CAN_F7R1_FB27_Pos (27U)
3488#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3489#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3490#define CAN_F7R1_FB28_Pos (28U)
3491#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3492#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3493#define CAN_F7R1_FB29_Pos (29U)
3494#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3495#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3496#define CAN_F7R1_FB30_Pos (30U)
3497#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3498#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3499#define CAN_F7R1_FB31_Pos (31U)
3500#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3501#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3502
3503/******************* Bit definition for CAN_F8R1 register *******************/
3504#define CAN_F8R1_FB0_Pos (0U)
3505#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3506#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3507#define CAN_F8R1_FB1_Pos (1U)
3508#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3509#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3510#define CAN_F8R1_FB2_Pos (2U)
3511#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3512#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3513#define CAN_F8R1_FB3_Pos (3U)
3514#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3515#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3516#define CAN_F8R1_FB4_Pos (4U)
3517#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3518#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3519#define CAN_F8R1_FB5_Pos (5U)
3520#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3521#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3522#define CAN_F8R1_FB6_Pos (6U)
3523#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3524#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3525#define CAN_F8R1_FB7_Pos (7U)
3526#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3527#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3528#define CAN_F8R1_FB8_Pos (8U)
3529#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3530#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3531#define CAN_F8R1_FB9_Pos (9U)
3532#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3533#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3534#define CAN_F8R1_FB10_Pos (10U)
3535#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3536#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3537#define CAN_F8R1_FB11_Pos (11U)
3538#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3539#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3540#define CAN_F8R1_FB12_Pos (12U)
3541#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3542#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3543#define CAN_F8R1_FB13_Pos (13U)
3544#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3545#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3546#define CAN_F8R1_FB14_Pos (14U)
3547#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3548#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3549#define CAN_F8R1_FB15_Pos (15U)
3550#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3551#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3552#define CAN_F8R1_FB16_Pos (16U)
3553#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3554#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3555#define CAN_F8R1_FB17_Pos (17U)
3556#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3557#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3558#define CAN_F8R1_FB18_Pos (18U)
3559#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3560#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3561#define CAN_F8R1_FB19_Pos (19U)
3562#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3563#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3564#define CAN_F8R1_FB20_Pos (20U)
3565#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3566#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3567#define CAN_F8R1_FB21_Pos (21U)
3568#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3569#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3570#define CAN_F8R1_FB22_Pos (22U)
3571#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3572#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3573#define CAN_F8R1_FB23_Pos (23U)
3574#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3575#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3576#define CAN_F8R1_FB24_Pos (24U)
3577#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3578#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3579#define CAN_F8R1_FB25_Pos (25U)
3580#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3581#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3582#define CAN_F8R1_FB26_Pos (26U)
3583#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3584#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3585#define CAN_F8R1_FB27_Pos (27U)
3586#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3587#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3588#define CAN_F8R1_FB28_Pos (28U)
3589#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3590#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3591#define CAN_F8R1_FB29_Pos (29U)
3592#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3593#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3594#define CAN_F8R1_FB30_Pos (30U)
3595#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3596#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3597#define CAN_F8R1_FB31_Pos (31U)
3598#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3599#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3600
3601/******************* Bit definition for CAN_F9R1 register *******************/
3602#define CAN_F9R1_FB0_Pos (0U)
3603#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3604#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3605#define CAN_F9R1_FB1_Pos (1U)
3606#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3607#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3608#define CAN_F9R1_FB2_Pos (2U)
3609#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3610#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3611#define CAN_F9R1_FB3_Pos (3U)
3612#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3613#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3614#define CAN_F9R1_FB4_Pos (4U)
3615#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3616#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3617#define CAN_F9R1_FB5_Pos (5U)
3618#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3619#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3620#define CAN_F9R1_FB6_Pos (6U)
3621#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3622#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3623#define CAN_F9R1_FB7_Pos (7U)
3624#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3625#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3626#define CAN_F9R1_FB8_Pos (8U)
3627#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3628#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3629#define CAN_F9R1_FB9_Pos (9U)
3630#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3631#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3632#define CAN_F9R1_FB10_Pos (10U)
3633#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3634#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3635#define CAN_F9R1_FB11_Pos (11U)
3636#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3637#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3638#define CAN_F9R1_FB12_Pos (12U)
3639#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3640#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3641#define CAN_F9R1_FB13_Pos (13U)
3642#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3643#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3644#define CAN_F9R1_FB14_Pos (14U)
3645#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3646#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3647#define CAN_F9R1_FB15_Pos (15U)
3648#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3649#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3650#define CAN_F9R1_FB16_Pos (16U)
3651#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3652#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3653#define CAN_F9R1_FB17_Pos (17U)
3654#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3655#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3656#define CAN_F9R1_FB18_Pos (18U)
3657#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3658#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3659#define CAN_F9R1_FB19_Pos (19U)
3660#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3661#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3662#define CAN_F9R1_FB20_Pos (20U)
3663#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3664#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3665#define CAN_F9R1_FB21_Pos (21U)
3666#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3667#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3668#define CAN_F9R1_FB22_Pos (22U)
3669#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3670#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3671#define CAN_F9R1_FB23_Pos (23U)
3672#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3673#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3674#define CAN_F9R1_FB24_Pos (24U)
3675#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3676#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3677#define CAN_F9R1_FB25_Pos (25U)
3678#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3679#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3680#define CAN_F9R1_FB26_Pos (26U)
3681#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3682#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3683#define CAN_F9R1_FB27_Pos (27U)
3684#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3685#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3686#define CAN_F9R1_FB28_Pos (28U)
3687#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3688#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3689#define CAN_F9R1_FB29_Pos (29U)
3690#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3691#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3692#define CAN_F9R1_FB30_Pos (30U)
3693#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3694#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3695#define CAN_F9R1_FB31_Pos (31U)
3696#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3697#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3698
3699/******************* Bit definition for CAN_F10R1 register ******************/
3700#define CAN_F10R1_FB0_Pos (0U)
3701#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3702#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3703#define CAN_F10R1_FB1_Pos (1U)
3704#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3705#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3706#define CAN_F10R1_FB2_Pos (2U)
3707#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3708#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3709#define CAN_F10R1_FB3_Pos (3U)
3710#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3711#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3712#define CAN_F10R1_FB4_Pos (4U)
3713#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3714#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3715#define CAN_F10R1_FB5_Pos (5U)
3716#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3717#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3718#define CAN_F10R1_FB6_Pos (6U)
3719#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3720#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3721#define CAN_F10R1_FB7_Pos (7U)
3722#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3723#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3724#define CAN_F10R1_FB8_Pos (8U)
3725#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
3726#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
3727#define CAN_F10R1_FB9_Pos (9U)
3728#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
3729#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
3730#define CAN_F10R1_FB10_Pos (10U)
3731#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
3732#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
3733#define CAN_F10R1_FB11_Pos (11U)
3734#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
3735#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
3736#define CAN_F10R1_FB12_Pos (12U)
3737#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
3738#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
3739#define CAN_F10R1_FB13_Pos (13U)
3740#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
3741#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
3742#define CAN_F10R1_FB14_Pos (14U)
3743#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
3744#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
3745#define CAN_F10R1_FB15_Pos (15U)
3746#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
3747#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
3748#define CAN_F10R1_FB16_Pos (16U)
3749#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
3750#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
3751#define CAN_F10R1_FB17_Pos (17U)
3752#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
3753#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
3754#define CAN_F10R1_FB18_Pos (18U)
3755#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
3756#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
3757#define CAN_F10R1_FB19_Pos (19U)
3758#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
3759#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
3760#define CAN_F10R1_FB20_Pos (20U)
3761#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
3762#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
3763#define CAN_F10R1_FB21_Pos (21U)
3764#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
3765#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
3766#define CAN_F10R1_FB22_Pos (22U)
3767#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
3768#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
3769#define CAN_F10R1_FB23_Pos (23U)
3770#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
3771#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
3772#define CAN_F10R1_FB24_Pos (24U)
3773#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
3774#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
3775#define CAN_F10R1_FB25_Pos (25U)
3776#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
3777#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
3778#define CAN_F10R1_FB26_Pos (26U)
3779#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
3780#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
3781#define CAN_F10R1_FB27_Pos (27U)
3782#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
3783#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
3784#define CAN_F10R1_FB28_Pos (28U)
3785#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
3786#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
3787#define CAN_F10R1_FB29_Pos (29U)
3788#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
3789#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
3790#define CAN_F10R1_FB30_Pos (30U)
3791#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
3792#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
3793#define CAN_F10R1_FB31_Pos (31U)
3794#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
3795#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
3796
3797/******************* Bit definition for CAN_F11R1 register ******************/
3798#define CAN_F11R1_FB0_Pos (0U)
3799#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
3800#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
3801#define CAN_F11R1_FB1_Pos (1U)
3802#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
3803#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
3804#define CAN_F11R1_FB2_Pos (2U)
3805#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
3806#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
3807#define CAN_F11R1_FB3_Pos (3U)
3808#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
3809#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
3810#define CAN_F11R1_FB4_Pos (4U)
3811#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
3812#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
3813#define CAN_F11R1_FB5_Pos (5U)
3814#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
3815#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
3816#define CAN_F11R1_FB6_Pos (6U)
3817#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
3818#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
3819#define CAN_F11R1_FB7_Pos (7U)
3820#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
3821#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
3822#define CAN_F11R1_FB8_Pos (8U)
3823#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
3824#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
3825#define CAN_F11R1_FB9_Pos (9U)
3826#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
3827#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
3828#define CAN_F11R1_FB10_Pos (10U)
3829#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
3830#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
3831#define CAN_F11R1_FB11_Pos (11U)
3832#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
3833#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
3834#define CAN_F11R1_FB12_Pos (12U)
3835#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
3836#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
3837#define CAN_F11R1_FB13_Pos (13U)
3838#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
3839#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
3840#define CAN_F11R1_FB14_Pos (14U)
3841#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
3842#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
3843#define CAN_F11R1_FB15_Pos (15U)
3844#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
3845#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
3846#define CAN_F11R1_FB16_Pos (16U)
3847#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
3848#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
3849#define CAN_F11R1_FB17_Pos (17U)
3850#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
3851#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
3852#define CAN_F11R1_FB18_Pos (18U)
3853#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
3854#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
3855#define CAN_F11R1_FB19_Pos (19U)
3856#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
3857#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
3858#define CAN_F11R1_FB20_Pos (20U)
3859#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
3860#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
3861#define CAN_F11R1_FB21_Pos (21U)
3862#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
3863#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
3864#define CAN_F11R1_FB22_Pos (22U)
3865#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
3866#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
3867#define CAN_F11R1_FB23_Pos (23U)
3868#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
3869#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
3870#define CAN_F11R1_FB24_Pos (24U)
3871#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
3872#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
3873#define CAN_F11R1_FB25_Pos (25U)
3874#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
3875#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
3876#define CAN_F11R1_FB26_Pos (26U)
3877#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
3878#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
3879#define CAN_F11R1_FB27_Pos (27U)
3880#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
3881#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
3882#define CAN_F11R1_FB28_Pos (28U)
3883#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
3884#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
3885#define CAN_F11R1_FB29_Pos (29U)
3886#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
3887#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
3888#define CAN_F11R1_FB30_Pos (30U)
3889#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
3890#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
3891#define CAN_F11R1_FB31_Pos (31U)
3892#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
3893#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
3894
3895/******************* Bit definition for CAN_F12R1 register ******************/
3896#define CAN_F12R1_FB0_Pos (0U)
3897#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
3898#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
3899#define CAN_F12R1_FB1_Pos (1U)
3900#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
3901#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
3902#define CAN_F12R1_FB2_Pos (2U)
3903#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
3904#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
3905#define CAN_F12R1_FB3_Pos (3U)
3906#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
3907#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
3908#define CAN_F12R1_FB4_Pos (4U)
3909#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
3910#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
3911#define CAN_F12R1_FB5_Pos (5U)
3912#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
3913#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
3914#define CAN_F12R1_FB6_Pos (6U)
3915#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
3916#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
3917#define CAN_F12R1_FB7_Pos (7U)
3918#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
3919#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
3920#define CAN_F12R1_FB8_Pos (8U)
3921#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
3922#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
3923#define CAN_F12R1_FB9_Pos (9U)
3924#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
3925#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
3926#define CAN_F12R1_FB10_Pos (10U)
3927#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
3928#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
3929#define CAN_F12R1_FB11_Pos (11U)
3930#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
3931#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
3932#define CAN_F12R1_FB12_Pos (12U)
3933#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
3934#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
3935#define CAN_F12R1_FB13_Pos (13U)
3936#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
3937#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
3938#define CAN_F12R1_FB14_Pos (14U)
3939#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
3940#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
3941#define CAN_F12R1_FB15_Pos (15U)
3942#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
3943#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
3944#define CAN_F12R1_FB16_Pos (16U)
3945#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
3946#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
3947#define CAN_F12R1_FB17_Pos (17U)
3948#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
3949#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
3950#define CAN_F12R1_FB18_Pos (18U)
3951#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
3952#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
3953#define CAN_F12R1_FB19_Pos (19U)
3954#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
3955#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
3956#define CAN_F12R1_FB20_Pos (20U)
3957#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
3958#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
3959#define CAN_F12R1_FB21_Pos (21U)
3960#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
3961#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
3962#define CAN_F12R1_FB22_Pos (22U)
3963#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
3964#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
3965#define CAN_F12R1_FB23_Pos (23U)
3966#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
3967#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
3968#define CAN_F12R1_FB24_Pos (24U)
3969#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
3970#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
3971#define CAN_F12R1_FB25_Pos (25U)
3972#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
3973#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
3974#define CAN_F12R1_FB26_Pos (26U)
3975#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
3976#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
3977#define CAN_F12R1_FB27_Pos (27U)
3978#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
3979#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
3980#define CAN_F12R1_FB28_Pos (28U)
3981#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
3982#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
3983#define CAN_F12R1_FB29_Pos (29U)
3984#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
3985#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
3986#define CAN_F12R1_FB30_Pos (30U)
3987#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
3988#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
3989#define CAN_F12R1_FB31_Pos (31U)
3990#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
3991#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
3992
3993/******************* Bit definition for CAN_F13R1 register ******************/
3994#define CAN_F13R1_FB0_Pos (0U)
3995#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
3996#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
3997#define CAN_F13R1_FB1_Pos (1U)
3998#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
3999#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
4000#define CAN_F13R1_FB2_Pos (2U)
4001#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
4002#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
4003#define CAN_F13R1_FB3_Pos (3U)
4004#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
4005#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
4006#define CAN_F13R1_FB4_Pos (4U)
4007#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
4008#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
4009#define CAN_F13R1_FB5_Pos (5U)
4010#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
4011#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
4012#define CAN_F13R1_FB6_Pos (6U)
4013#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
4014#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
4015#define CAN_F13R1_FB7_Pos (7U)
4016#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
4017#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
4018#define CAN_F13R1_FB8_Pos (8U)
4019#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
4020#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
4021#define CAN_F13R1_FB9_Pos (9U)
4022#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
4023#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
4024#define CAN_F13R1_FB10_Pos (10U)
4025#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
4026#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
4027#define CAN_F13R1_FB11_Pos (11U)
4028#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
4029#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
4030#define CAN_F13R1_FB12_Pos (12U)
4031#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
4032#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
4033#define CAN_F13R1_FB13_Pos (13U)
4034#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
4035#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
4036#define CAN_F13R1_FB14_Pos (14U)
4037#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
4038#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
4039#define CAN_F13R1_FB15_Pos (15U)
4040#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
4041#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4042#define CAN_F13R1_FB16_Pos (16U)
4043#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4044#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4045#define CAN_F13R1_FB17_Pos (17U)
4046#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4047#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4048#define CAN_F13R1_FB18_Pos (18U)
4049#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4050#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4051#define CAN_F13R1_FB19_Pos (19U)
4052#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4053#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4054#define CAN_F13R1_FB20_Pos (20U)
4055#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4056#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4057#define CAN_F13R1_FB21_Pos (21U)
4058#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4059#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4060#define CAN_F13R1_FB22_Pos (22U)
4061#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4062#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4063#define CAN_F13R1_FB23_Pos (23U)
4064#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4065#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4066#define CAN_F13R1_FB24_Pos (24U)
4067#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4068#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4069#define CAN_F13R1_FB25_Pos (25U)
4070#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4071#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4072#define CAN_F13R1_FB26_Pos (26U)
4073#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4074#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4075#define CAN_F13R1_FB27_Pos (27U)
4076#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4077#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4078#define CAN_F13R1_FB28_Pos (28U)
4079#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4080#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4081#define CAN_F13R1_FB29_Pos (29U)
4082#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4083#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4084#define CAN_F13R1_FB30_Pos (30U)
4085#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4086#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4087#define CAN_F13R1_FB31_Pos (31U)
4088#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4089#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4090
4091/******************* Bit definition for CAN_F0R2 register *******************/
4092#define CAN_F0R2_FB0_Pos (0U)
4093#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4094#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4095#define CAN_F0R2_FB1_Pos (1U)
4096#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4097#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4098#define CAN_F0R2_FB2_Pos (2U)
4099#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4100#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4101#define CAN_F0R2_FB3_Pos (3U)
4102#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4103#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4104#define CAN_F0R2_FB4_Pos (4U)
4105#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4106#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4107#define CAN_F0R2_FB5_Pos (5U)
4108#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4109#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4110#define CAN_F0R2_FB6_Pos (6U)
4111#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4112#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4113#define CAN_F0R2_FB7_Pos (7U)
4114#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4115#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4116#define CAN_F0R2_FB8_Pos (8U)
4117#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4118#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4119#define CAN_F0R2_FB9_Pos (9U)
4120#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4121#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4122#define CAN_F0R2_FB10_Pos (10U)
4123#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4124#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4125#define CAN_F0R2_FB11_Pos (11U)
4126#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4127#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4128#define CAN_F0R2_FB12_Pos (12U)
4129#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4130#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4131#define CAN_F0R2_FB13_Pos (13U)
4132#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4133#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4134#define CAN_F0R2_FB14_Pos (14U)
4135#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4136#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4137#define CAN_F0R2_FB15_Pos (15U)
4138#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4139#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4140#define CAN_F0R2_FB16_Pos (16U)
4141#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4142#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4143#define CAN_F0R2_FB17_Pos (17U)
4144#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4145#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4146#define CAN_F0R2_FB18_Pos (18U)
4147#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4148#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4149#define CAN_F0R2_FB19_Pos (19U)
4150#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4151#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4152#define CAN_F0R2_FB20_Pos (20U)
4153#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4154#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4155#define CAN_F0R2_FB21_Pos (21U)
4156#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4157#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4158#define CAN_F0R2_FB22_Pos (22U)
4159#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4160#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4161#define CAN_F0R2_FB23_Pos (23U)
4162#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4163#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4164#define CAN_F0R2_FB24_Pos (24U)
4165#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4166#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4167#define CAN_F0R2_FB25_Pos (25U)
4168#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4169#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4170#define CAN_F0R2_FB26_Pos (26U)
4171#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4172#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4173#define CAN_F0R2_FB27_Pos (27U)
4174#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4175#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4176#define CAN_F0R2_FB28_Pos (28U)
4177#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4178#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4179#define CAN_F0R2_FB29_Pos (29U)
4180#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4181#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4182#define CAN_F0R2_FB30_Pos (30U)
4183#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4184#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4185#define CAN_F0R2_FB31_Pos (31U)
4186#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4187#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4188
4189/******************* Bit definition for CAN_F1R2 register *******************/
4190#define CAN_F1R2_FB0_Pos (0U)
4191#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4192#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4193#define CAN_F1R2_FB1_Pos (1U)
4194#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4195#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4196#define CAN_F1R2_FB2_Pos (2U)
4197#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4198#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4199#define CAN_F1R2_FB3_Pos (3U)
4200#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4201#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4202#define CAN_F1R2_FB4_Pos (4U)
4203#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4204#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4205#define CAN_F1R2_FB5_Pos (5U)
4206#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4207#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4208#define CAN_F1R2_FB6_Pos (6U)
4209#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4210#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4211#define CAN_F1R2_FB7_Pos (7U)
4212#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4213#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4214#define CAN_F1R2_FB8_Pos (8U)
4215#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4216#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4217#define CAN_F1R2_FB9_Pos (9U)
4218#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4219#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4220#define CAN_F1R2_FB10_Pos (10U)
4221#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4222#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4223#define CAN_F1R2_FB11_Pos (11U)
4224#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4225#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4226#define CAN_F1R2_FB12_Pos (12U)
4227#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4228#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4229#define CAN_F1R2_FB13_Pos (13U)
4230#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4231#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4232#define CAN_F1R2_FB14_Pos (14U)
4233#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4234#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4235#define CAN_F1R2_FB15_Pos (15U)
4236#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4237#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4238#define CAN_F1R2_FB16_Pos (16U)
4239#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4240#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4241#define CAN_F1R2_FB17_Pos (17U)
4242#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4243#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4244#define CAN_F1R2_FB18_Pos (18U)
4245#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4246#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4247#define CAN_F1R2_FB19_Pos (19U)
4248#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4249#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4250#define CAN_F1R2_FB20_Pos (20U)
4251#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4252#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4253#define CAN_F1R2_FB21_Pos (21U)
4254#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4255#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4256#define CAN_F1R2_FB22_Pos (22U)
4257#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4258#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4259#define CAN_F1R2_FB23_Pos (23U)
4260#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4261#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4262#define CAN_F1R2_FB24_Pos (24U)
4263#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4264#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4265#define CAN_F1R2_FB25_Pos (25U)
4266#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4267#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4268#define CAN_F1R2_FB26_Pos (26U)
4269#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4270#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4271#define CAN_F1R2_FB27_Pos (27U)
4272#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4273#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4274#define CAN_F1R2_FB28_Pos (28U)
4275#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4276#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4277#define CAN_F1R2_FB29_Pos (29U)
4278#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4279#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4280#define CAN_F1R2_FB30_Pos (30U)
4281#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4282#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4283#define CAN_F1R2_FB31_Pos (31U)
4284#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4285#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4286
4287/******************* Bit definition for CAN_F2R2 register *******************/
4288#define CAN_F2R2_FB0_Pos (0U)
4289#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4290#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4291#define CAN_F2R2_FB1_Pos (1U)
4292#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4293#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4294#define CAN_F2R2_FB2_Pos (2U)
4295#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4296#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4297#define CAN_F2R2_FB3_Pos (3U)
4298#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4299#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4300#define CAN_F2R2_FB4_Pos (4U)
4301#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4302#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4303#define CAN_F2R2_FB5_Pos (5U)
4304#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4305#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4306#define CAN_F2R2_FB6_Pos (6U)
4307#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4308#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4309#define CAN_F2R2_FB7_Pos (7U)
4310#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4311#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4312#define CAN_F2R2_FB8_Pos (8U)
4313#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4314#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4315#define CAN_F2R2_FB9_Pos (9U)
4316#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4317#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4318#define CAN_F2R2_FB10_Pos (10U)
4319#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4320#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4321#define CAN_F2R2_FB11_Pos (11U)
4322#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4323#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4324#define CAN_F2R2_FB12_Pos (12U)
4325#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4326#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4327#define CAN_F2R2_FB13_Pos (13U)
4328#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4329#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4330#define CAN_F2R2_FB14_Pos (14U)
4331#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4332#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4333#define CAN_F2R2_FB15_Pos (15U)
4334#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4335#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4336#define CAN_F2R2_FB16_Pos (16U)
4337#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4338#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4339#define CAN_F2R2_FB17_Pos (17U)
4340#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4341#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4342#define CAN_F2R2_FB18_Pos (18U)
4343#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4344#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4345#define CAN_F2R2_FB19_Pos (19U)
4346#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4347#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4348#define CAN_F2R2_FB20_Pos (20U)
4349#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4350#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4351#define CAN_F2R2_FB21_Pos (21U)
4352#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4353#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4354#define CAN_F2R2_FB22_Pos (22U)
4355#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4356#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4357#define CAN_F2R2_FB23_Pos (23U)
4358#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4359#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4360#define CAN_F2R2_FB24_Pos (24U)
4361#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4362#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4363#define CAN_F2R2_FB25_Pos (25U)
4364#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4365#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4366#define CAN_F2R2_FB26_Pos (26U)
4367#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4368#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4369#define CAN_F2R2_FB27_Pos (27U)
4370#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4371#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4372#define CAN_F2R2_FB28_Pos (28U)
4373#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4374#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4375#define CAN_F2R2_FB29_Pos (29U)
4376#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4377#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4378#define CAN_F2R2_FB30_Pos (30U)
4379#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4380#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4381#define CAN_F2R2_FB31_Pos (31U)
4382#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4383#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4384
4385/******************* Bit definition for CAN_F3R2 register *******************/
4386#define CAN_F3R2_FB0_Pos (0U)
4387#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4388#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4389#define CAN_F3R2_FB1_Pos (1U)
4390#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4391#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4392#define CAN_F3R2_FB2_Pos (2U)
4393#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4394#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4395#define CAN_F3R2_FB3_Pos (3U)
4396#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4397#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4398#define CAN_F3R2_FB4_Pos (4U)
4399#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4400#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4401#define CAN_F3R2_FB5_Pos (5U)
4402#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4403#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4404#define CAN_F3R2_FB6_Pos (6U)
4405#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4406#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4407#define CAN_F3R2_FB7_Pos (7U)
4408#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4409#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4410#define CAN_F3R2_FB8_Pos (8U)
4411#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4412#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4413#define CAN_F3R2_FB9_Pos (9U)
4414#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4415#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4416#define CAN_F3R2_FB10_Pos (10U)
4417#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4418#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4419#define CAN_F3R2_FB11_Pos (11U)
4420#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4421#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4422#define CAN_F3R2_FB12_Pos (12U)
4423#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4424#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4425#define CAN_F3R2_FB13_Pos (13U)
4426#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4427#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4428#define CAN_F3R2_FB14_Pos (14U)
4429#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4430#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4431#define CAN_F3R2_FB15_Pos (15U)
4432#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4433#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4434#define CAN_F3R2_FB16_Pos (16U)
4435#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4436#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4437#define CAN_F3R2_FB17_Pos (17U)
4438#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4439#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4440#define CAN_F3R2_FB18_Pos (18U)
4441#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4442#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4443#define CAN_F3R2_FB19_Pos (19U)
4444#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4445#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4446#define CAN_F3R2_FB20_Pos (20U)
4447#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4448#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4449#define CAN_F3R2_FB21_Pos (21U)
4450#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4451#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4452#define CAN_F3R2_FB22_Pos (22U)
4453#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4454#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4455#define CAN_F3R2_FB23_Pos (23U)
4456#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4457#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4458#define CAN_F3R2_FB24_Pos (24U)
4459#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4460#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4461#define CAN_F3R2_FB25_Pos (25U)
4462#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4463#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4464#define CAN_F3R2_FB26_Pos (26U)
4465#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4466#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4467#define CAN_F3R2_FB27_Pos (27U)
4468#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4469#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4470#define CAN_F3R2_FB28_Pos (28U)
4471#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4472#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4473#define CAN_F3R2_FB29_Pos (29U)
4474#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4475#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4476#define CAN_F3R2_FB30_Pos (30U)
4477#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4478#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4479#define CAN_F3R2_FB31_Pos (31U)
4480#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4481#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4482
4483/******************* Bit definition for CAN_F4R2 register *******************/
4484#define CAN_F4R2_FB0_Pos (0U)
4485#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4486#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4487#define CAN_F4R2_FB1_Pos (1U)
4488#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4489#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4490#define CAN_F4R2_FB2_Pos (2U)
4491#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4492#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4493#define CAN_F4R2_FB3_Pos (3U)
4494#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4495#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4496#define CAN_F4R2_FB4_Pos (4U)
4497#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4498#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4499#define CAN_F4R2_FB5_Pos (5U)
4500#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4501#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4502#define CAN_F4R2_FB6_Pos (6U)
4503#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4504#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4505#define CAN_F4R2_FB7_Pos (7U)
4506#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4507#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4508#define CAN_F4R2_FB8_Pos (8U)
4509#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4510#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4511#define CAN_F4R2_FB9_Pos (9U)
4512#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4513#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4514#define CAN_F4R2_FB10_Pos (10U)
4515#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4516#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4517#define CAN_F4R2_FB11_Pos (11U)
4518#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4519#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4520#define CAN_F4R2_FB12_Pos (12U)
4521#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4522#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4523#define CAN_F4R2_FB13_Pos (13U)
4524#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4525#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4526#define CAN_F4R2_FB14_Pos (14U)
4527#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4528#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4529#define CAN_F4R2_FB15_Pos (15U)
4530#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4531#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4532#define CAN_F4R2_FB16_Pos (16U)
4533#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4534#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4535#define CAN_F4R2_FB17_Pos (17U)
4536#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4537#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4538#define CAN_F4R2_FB18_Pos (18U)
4539#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4540#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4541#define CAN_F4R2_FB19_Pos (19U)
4542#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4543#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4544#define CAN_F4R2_FB20_Pos (20U)
4545#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4546#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4547#define CAN_F4R2_FB21_Pos (21U)
4548#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4549#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4550#define CAN_F4R2_FB22_Pos (22U)
4551#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4552#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4553#define CAN_F4R2_FB23_Pos (23U)
4554#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4555#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4556#define CAN_F4R2_FB24_Pos (24U)
4557#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4558#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4559#define CAN_F4R2_FB25_Pos (25U)
4560#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4561#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4562#define CAN_F4R2_FB26_Pos (26U)
4563#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4564#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4565#define CAN_F4R2_FB27_Pos (27U)
4566#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4567#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4568#define CAN_F4R2_FB28_Pos (28U)
4569#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4570#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4571#define CAN_F4R2_FB29_Pos (29U)
4572#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4573#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4574#define CAN_F4R2_FB30_Pos (30U)
4575#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4576#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4577#define CAN_F4R2_FB31_Pos (31U)
4578#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4579#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4580
4581/******************* Bit definition for CAN_F5R2 register *******************/
4582#define CAN_F5R2_FB0_Pos (0U)
4583#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4584#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4585#define CAN_F5R2_FB1_Pos (1U)
4586#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4587#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4588#define CAN_F5R2_FB2_Pos (2U)
4589#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4590#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4591#define CAN_F5R2_FB3_Pos (3U)
4592#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4593#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4594#define CAN_F5R2_FB4_Pos (4U)
4595#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4596#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4597#define CAN_F5R2_FB5_Pos (5U)
4598#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4599#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4600#define CAN_F5R2_FB6_Pos (6U)
4601#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4602#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4603#define CAN_F5R2_FB7_Pos (7U)
4604#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4605#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4606#define CAN_F5R2_FB8_Pos (8U)
4607#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4608#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4609#define CAN_F5R2_FB9_Pos (9U)
4610#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4611#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4612#define CAN_F5R2_FB10_Pos (10U)
4613#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4614#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4615#define CAN_F5R2_FB11_Pos (11U)
4616#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4617#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4618#define CAN_F5R2_FB12_Pos (12U)
4619#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4620#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4621#define CAN_F5R2_FB13_Pos (13U)
4622#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4623#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4624#define CAN_F5R2_FB14_Pos (14U)
4625#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4626#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4627#define CAN_F5R2_FB15_Pos (15U)
4628#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4629#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4630#define CAN_F5R2_FB16_Pos (16U)
4631#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4632#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4633#define CAN_F5R2_FB17_Pos (17U)
4634#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4635#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4636#define CAN_F5R2_FB18_Pos (18U)
4637#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4638#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4639#define CAN_F5R2_FB19_Pos (19U)
4640#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4641#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4642#define CAN_F5R2_FB20_Pos (20U)
4643#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4644#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4645#define CAN_F5R2_FB21_Pos (21U)
4646#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4647#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4648#define CAN_F5R2_FB22_Pos (22U)
4649#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4650#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4651#define CAN_F5R2_FB23_Pos (23U)
4652#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4653#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4654#define CAN_F5R2_FB24_Pos (24U)
4655#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4656#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4657#define CAN_F5R2_FB25_Pos (25U)
4658#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4659#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4660#define CAN_F5R2_FB26_Pos (26U)
4661#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4662#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4663#define CAN_F5R2_FB27_Pos (27U)
4664#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4665#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4666#define CAN_F5R2_FB28_Pos (28U)
4667#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4668#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4669#define CAN_F5R2_FB29_Pos (29U)
4670#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4671#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4672#define CAN_F5R2_FB30_Pos (30U)
4673#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4674#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4675#define CAN_F5R2_FB31_Pos (31U)
4676#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4677#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4678
4679/******************* Bit definition for CAN_F6R2 register *******************/
4680#define CAN_F6R2_FB0_Pos (0U)
4681#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4682#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4683#define CAN_F6R2_FB1_Pos (1U)
4684#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4685#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4686#define CAN_F6R2_FB2_Pos (2U)
4687#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4688#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4689#define CAN_F6R2_FB3_Pos (3U)
4690#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4691#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4692#define CAN_F6R2_FB4_Pos (4U)
4693#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4694#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4695#define CAN_F6R2_FB5_Pos (5U)
4696#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4697#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4698#define CAN_F6R2_FB6_Pos (6U)
4699#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4700#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4701#define CAN_F6R2_FB7_Pos (7U)
4702#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4703#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4704#define CAN_F6R2_FB8_Pos (8U)
4705#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4706#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4707#define CAN_F6R2_FB9_Pos (9U)
4708#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4709#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4710#define CAN_F6R2_FB10_Pos (10U)
4711#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4712#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4713#define CAN_F6R2_FB11_Pos (11U)
4714#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4715#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4716#define CAN_F6R2_FB12_Pos (12U)
4717#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4718#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4719#define CAN_F6R2_FB13_Pos (13U)
4720#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4721#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4722#define CAN_F6R2_FB14_Pos (14U)
4723#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4724#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
4725#define CAN_F6R2_FB15_Pos (15U)
4726#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
4727#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
4728#define CAN_F6R2_FB16_Pos (16U)
4729#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
4730#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
4731#define CAN_F6R2_FB17_Pos (17U)
4732#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
4733#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
4734#define CAN_F6R2_FB18_Pos (18U)
4735#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
4736#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
4737#define CAN_F6R2_FB19_Pos (19U)
4738#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
4739#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
4740#define CAN_F6R2_FB20_Pos (20U)
4741#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
4742#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
4743#define CAN_F6R2_FB21_Pos (21U)
4744#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
4745#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
4746#define CAN_F6R2_FB22_Pos (22U)
4747#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
4748#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
4749#define CAN_F6R2_FB23_Pos (23U)
4750#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
4751#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
4752#define CAN_F6R2_FB24_Pos (24U)
4753#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
4754#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
4755#define CAN_F6R2_FB25_Pos (25U)
4756#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
4757#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
4758#define CAN_F6R2_FB26_Pos (26U)
4759#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
4760#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
4761#define CAN_F6R2_FB27_Pos (27U)
4762#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
4763#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
4764#define CAN_F6R2_FB28_Pos (28U)
4765#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
4766#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
4767#define CAN_F6R2_FB29_Pos (29U)
4768#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
4769#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
4770#define CAN_F6R2_FB30_Pos (30U)
4771#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
4772#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
4773#define CAN_F6R2_FB31_Pos (31U)
4774#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
4775#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
4776
4777/******************* Bit definition for CAN_F7R2 register *******************/
4778#define CAN_F7R2_FB0_Pos (0U)
4779#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
4780#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
4781#define CAN_F7R2_FB1_Pos (1U)
4782#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
4783#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
4784#define CAN_F7R2_FB2_Pos (2U)
4785#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
4786#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
4787#define CAN_F7R2_FB3_Pos (3U)
4788#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
4789#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
4790#define CAN_F7R2_FB4_Pos (4U)
4791#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
4792#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
4793#define CAN_F7R2_FB5_Pos (5U)
4794#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
4795#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
4796#define CAN_F7R2_FB6_Pos (6U)
4797#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
4798#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
4799#define CAN_F7R2_FB7_Pos (7U)
4800#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
4801#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
4802#define CAN_F7R2_FB8_Pos (8U)
4803#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
4804#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
4805#define CAN_F7R2_FB9_Pos (9U)
4806#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
4807#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
4808#define CAN_F7R2_FB10_Pos (10U)
4809#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
4810#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
4811#define CAN_F7R2_FB11_Pos (11U)
4812#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
4813#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
4814#define CAN_F7R2_FB12_Pos (12U)
4815#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
4816#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
4817#define CAN_F7R2_FB13_Pos (13U)
4818#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
4819#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
4820#define CAN_F7R2_FB14_Pos (14U)
4821#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
4822#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
4823#define CAN_F7R2_FB15_Pos (15U)
4824#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
4825#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
4826#define CAN_F7R2_FB16_Pos (16U)
4827#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
4828#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
4829#define CAN_F7R2_FB17_Pos (17U)
4830#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
4831#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
4832#define CAN_F7R2_FB18_Pos (18U)
4833#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
4834#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
4835#define CAN_F7R2_FB19_Pos (19U)
4836#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
4837#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
4838#define CAN_F7R2_FB20_Pos (20U)
4839#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
4840#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
4841#define CAN_F7R2_FB21_Pos (21U)
4842#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
4843#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
4844#define CAN_F7R2_FB22_Pos (22U)
4845#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
4846#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
4847#define CAN_F7R2_FB23_Pos (23U)
4848#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
4849#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
4850#define CAN_F7R2_FB24_Pos (24U)
4851#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
4852#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
4853#define CAN_F7R2_FB25_Pos (25U)
4854#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
4855#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
4856#define CAN_F7R2_FB26_Pos (26U)
4857#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
4858#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
4859#define CAN_F7R2_FB27_Pos (27U)
4860#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
4861#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
4862#define CAN_F7R2_FB28_Pos (28U)
4863#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
4864#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
4865#define CAN_F7R2_FB29_Pos (29U)
4866#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
4867#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
4868#define CAN_F7R2_FB30_Pos (30U)
4869#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
4870#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
4871#define CAN_F7R2_FB31_Pos (31U)
4872#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
4873#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
4874
4875/******************* Bit definition for CAN_F8R2 register *******************/
4876#define CAN_F8R2_FB0_Pos (0U)
4877#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
4878#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
4879#define CAN_F8R2_FB1_Pos (1U)
4880#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
4881#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
4882#define CAN_F8R2_FB2_Pos (2U)
4883#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
4884#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
4885#define CAN_F8R2_FB3_Pos (3U)
4886#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
4887#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
4888#define CAN_F8R2_FB4_Pos (4U)
4889#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
4890#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
4891#define CAN_F8R2_FB5_Pos (5U)
4892#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
4893#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
4894#define CAN_F8R2_FB6_Pos (6U)
4895#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
4896#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
4897#define CAN_F8R2_FB7_Pos (7U)
4898#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
4899#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
4900#define CAN_F8R2_FB8_Pos (8U)
4901#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
4902#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
4903#define CAN_F8R2_FB9_Pos (9U)
4904#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
4905#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
4906#define CAN_F8R2_FB10_Pos (10U)
4907#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
4908#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
4909#define CAN_F8R2_FB11_Pos (11U)
4910#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
4911#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
4912#define CAN_F8R2_FB12_Pos (12U)
4913#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
4914#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
4915#define CAN_F8R2_FB13_Pos (13U)
4916#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
4917#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
4918#define CAN_F8R2_FB14_Pos (14U)
4919#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
4920#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
4921#define CAN_F8R2_FB15_Pos (15U)
4922#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
4923#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
4924#define CAN_F8R2_FB16_Pos (16U)
4925#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
4926#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
4927#define CAN_F8R2_FB17_Pos (17U)
4928#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
4929#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
4930#define CAN_F8R2_FB18_Pos (18U)
4931#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
4932#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
4933#define CAN_F8R2_FB19_Pos (19U)
4934#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
4935#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
4936#define CAN_F8R2_FB20_Pos (20U)
4937#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
4938#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
4939#define CAN_F8R2_FB21_Pos (21U)
4940#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
4941#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
4942#define CAN_F8R2_FB22_Pos (22U)
4943#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
4944#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
4945#define CAN_F8R2_FB23_Pos (23U)
4946#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
4947#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
4948#define CAN_F8R2_FB24_Pos (24U)
4949#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
4950#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
4951#define CAN_F8R2_FB25_Pos (25U)
4952#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
4953#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
4954#define CAN_F8R2_FB26_Pos (26U)
4955#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
4956#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
4957#define CAN_F8R2_FB27_Pos (27U)
4958#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
4959#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
4960#define CAN_F8R2_FB28_Pos (28U)
4961#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
4962#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
4963#define CAN_F8R2_FB29_Pos (29U)
4964#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
4965#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
4966#define CAN_F8R2_FB30_Pos (30U)
4967#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
4968#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
4969#define CAN_F8R2_FB31_Pos (31U)
4970#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
4971#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
4972
4973/******************* Bit definition for CAN_F9R2 register *******************/
4974#define CAN_F9R2_FB0_Pos (0U)
4975#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
4976#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
4977#define CAN_F9R2_FB1_Pos (1U)
4978#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
4979#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
4980#define CAN_F9R2_FB2_Pos (2U)
4981#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
4982#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
4983#define CAN_F9R2_FB3_Pos (3U)
4984#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
4985#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
4986#define CAN_F9R2_FB4_Pos (4U)
4987#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
4988#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
4989#define CAN_F9R2_FB5_Pos (5U)
4990#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
4991#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
4992#define CAN_F9R2_FB6_Pos (6U)
4993#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
4994#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
4995#define CAN_F9R2_FB7_Pos (7U)
4996#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
4997#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
4998#define CAN_F9R2_FB8_Pos (8U)
4999#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
5000#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
5001#define CAN_F9R2_FB9_Pos (9U)
5002#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
5003#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
5004#define CAN_F9R2_FB10_Pos (10U)
5005#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
5006#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
5007#define CAN_F9R2_FB11_Pos (11U)
5008#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
5009#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
5010#define CAN_F9R2_FB12_Pos (12U)
5011#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
5012#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
5013#define CAN_F9R2_FB13_Pos (13U)
5014#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
5015#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
5016#define CAN_F9R2_FB14_Pos (14U)
5017#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
5018#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
5019#define CAN_F9R2_FB15_Pos (15U)
5020#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
5021#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
5022#define CAN_F9R2_FB16_Pos (16U)
5023#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
5024#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
5025#define CAN_F9R2_FB17_Pos (17U)
5026#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
5027#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
5028#define CAN_F9R2_FB18_Pos (18U)
5029#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
5030#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
5031#define CAN_F9R2_FB19_Pos (19U)
5032#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
5033#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
5034#define CAN_F9R2_FB20_Pos (20U)
5035#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
5036#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
5037#define CAN_F9R2_FB21_Pos (21U)
5038#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
5039#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
5040#define CAN_F9R2_FB22_Pos (22U)
5041#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5042#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5043#define CAN_F9R2_FB23_Pos (23U)
5044#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5045#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5046#define CAN_F9R2_FB24_Pos (24U)
5047#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5048#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5049#define CAN_F9R2_FB25_Pos (25U)
5050#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5051#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5052#define CAN_F9R2_FB26_Pos (26U)
5053#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5054#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5055#define CAN_F9R2_FB27_Pos (27U)
5056#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5057#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5058#define CAN_F9R2_FB28_Pos (28U)
5059#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5060#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5061#define CAN_F9R2_FB29_Pos (29U)
5062#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5063#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5064#define CAN_F9R2_FB30_Pos (30U)
5065#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5066#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5067#define CAN_F9R2_FB31_Pos (31U)
5068#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5069#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5070
5071/******************* Bit definition for CAN_F10R2 register ******************/
5072#define CAN_F10R2_FB0_Pos (0U)
5073#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5074#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5075#define CAN_F10R2_FB1_Pos (1U)
5076#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5077#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5078#define CAN_F10R2_FB2_Pos (2U)
5079#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5080#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5081#define CAN_F10R2_FB3_Pos (3U)
5082#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5083#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5084#define CAN_F10R2_FB4_Pos (4U)
5085#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5086#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5087#define CAN_F10R2_FB5_Pos (5U)
5088#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5089#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5090#define CAN_F10R2_FB6_Pos (6U)
5091#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5092#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5093#define CAN_F10R2_FB7_Pos (7U)
5094#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5095#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5096#define CAN_F10R2_FB8_Pos (8U)
5097#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5098#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5099#define CAN_F10R2_FB9_Pos (9U)
5100#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5101#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5102#define CAN_F10R2_FB10_Pos (10U)
5103#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5104#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5105#define CAN_F10R2_FB11_Pos (11U)
5106#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5107#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5108#define CAN_F10R2_FB12_Pos (12U)
5109#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5110#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5111#define CAN_F10R2_FB13_Pos (13U)
5112#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5113#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5114#define CAN_F10R2_FB14_Pos (14U)
5115#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5116#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5117#define CAN_F10R2_FB15_Pos (15U)
5118#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5119#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5120#define CAN_F10R2_FB16_Pos (16U)
5121#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5122#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5123#define CAN_F10R2_FB17_Pos (17U)
5124#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5125#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5126#define CAN_F10R2_FB18_Pos (18U)
5127#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5128#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5129#define CAN_F10R2_FB19_Pos (19U)
5130#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5131#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5132#define CAN_F10R2_FB20_Pos (20U)
5133#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5134#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5135#define CAN_F10R2_FB21_Pos (21U)
5136#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5137#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5138#define CAN_F10R2_FB22_Pos (22U)
5139#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5140#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5141#define CAN_F10R2_FB23_Pos (23U)
5142#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5143#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5144#define CAN_F10R2_FB24_Pos (24U)
5145#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5146#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5147#define CAN_F10R2_FB25_Pos (25U)
5148#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5149#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5150#define CAN_F10R2_FB26_Pos (26U)
5151#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5152#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5153#define CAN_F10R2_FB27_Pos (27U)
5154#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5155#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5156#define CAN_F10R2_FB28_Pos (28U)
5157#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5158#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5159#define CAN_F10R2_FB29_Pos (29U)
5160#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5161#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5162#define CAN_F10R2_FB30_Pos (30U)
5163#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5164#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5165#define CAN_F10R2_FB31_Pos (31U)
5166#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5167#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5168
5169/******************* Bit definition for CAN_F11R2 register ******************/
5170#define CAN_F11R2_FB0_Pos (0U)
5171#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5172#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5173#define CAN_F11R2_FB1_Pos (1U)
5174#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5175#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5176#define CAN_F11R2_FB2_Pos (2U)
5177#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5178#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5179#define CAN_F11R2_FB3_Pos (3U)
5180#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5181#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5182#define CAN_F11R2_FB4_Pos (4U)
5183#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5184#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5185#define CAN_F11R2_FB5_Pos (5U)
5186#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5187#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5188#define CAN_F11R2_FB6_Pos (6U)
5189#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5190#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5191#define CAN_F11R2_FB7_Pos (7U)
5192#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5193#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5194#define CAN_F11R2_FB8_Pos (8U)
5195#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5196#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5197#define CAN_F11R2_FB9_Pos (9U)
5198#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5199#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5200#define CAN_F11R2_FB10_Pos (10U)
5201#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5202#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5203#define CAN_F11R2_FB11_Pos (11U)
5204#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5205#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5206#define CAN_F11R2_FB12_Pos (12U)
5207#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5208#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5209#define CAN_F11R2_FB13_Pos (13U)
5210#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5211#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5212#define CAN_F11R2_FB14_Pos (14U)
5213#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5214#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5215#define CAN_F11R2_FB15_Pos (15U)
5216#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5217#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5218#define CAN_F11R2_FB16_Pos (16U)
5219#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5220#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5221#define CAN_F11R2_FB17_Pos (17U)
5222#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5223#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5224#define CAN_F11R2_FB18_Pos (18U)
5225#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5226#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5227#define CAN_F11R2_FB19_Pos (19U)
5228#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5229#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5230#define CAN_F11R2_FB20_Pos (20U)
5231#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5232#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5233#define CAN_F11R2_FB21_Pos (21U)
5234#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5235#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5236#define CAN_F11R2_FB22_Pos (22U)
5237#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5238#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5239#define CAN_F11R2_FB23_Pos (23U)
5240#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5241#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5242#define CAN_F11R2_FB24_Pos (24U)
5243#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5244#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5245#define CAN_F11R2_FB25_Pos (25U)
5246#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5247#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5248#define CAN_F11R2_FB26_Pos (26U)
5249#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5250#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5251#define CAN_F11R2_FB27_Pos (27U)
5252#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5253#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5254#define CAN_F11R2_FB28_Pos (28U)
5255#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5256#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5257#define CAN_F11R2_FB29_Pos (29U)
5258#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5259#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5260#define CAN_F11R2_FB30_Pos (30U)
5261#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5262#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5263#define CAN_F11R2_FB31_Pos (31U)
5264#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5265#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5266
5267/******************* Bit definition for CAN_F12R2 register ******************/
5268#define CAN_F12R2_FB0_Pos (0U)
5269#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5270#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5271#define CAN_F12R2_FB1_Pos (1U)
5272#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5273#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5274#define CAN_F12R2_FB2_Pos (2U)
5275#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5276#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5277#define CAN_F12R2_FB3_Pos (3U)
5278#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5279#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5280#define CAN_F12R2_FB4_Pos (4U)
5281#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5282#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5283#define CAN_F12R2_FB5_Pos (5U)
5284#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5285#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5286#define CAN_F12R2_FB6_Pos (6U)
5287#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5288#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5289#define CAN_F12R2_FB7_Pos (7U)
5290#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5291#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5292#define CAN_F12R2_FB8_Pos (8U)
5293#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5294#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5295#define CAN_F12R2_FB9_Pos (9U)
5296#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5297#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5298#define CAN_F12R2_FB10_Pos (10U)
5299#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5300#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5301#define CAN_F12R2_FB11_Pos (11U)
5302#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5303#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5304#define CAN_F12R2_FB12_Pos (12U)
5305#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5306#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5307#define CAN_F12R2_FB13_Pos (13U)
5308#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5309#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5310#define CAN_F12R2_FB14_Pos (14U)
5311#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5312#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5313#define CAN_F12R2_FB15_Pos (15U)
5314#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5315#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5316#define CAN_F12R2_FB16_Pos (16U)
5317#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5318#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5319#define CAN_F12R2_FB17_Pos (17U)
5320#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5321#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5322#define CAN_F12R2_FB18_Pos (18U)
5323#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5324#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5325#define CAN_F12R2_FB19_Pos (19U)
5326#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5327#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5328#define CAN_F12R2_FB20_Pos (20U)
5329#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5330#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5331#define CAN_F12R2_FB21_Pos (21U)
5332#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5333#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5334#define CAN_F12R2_FB22_Pos (22U)
5335#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5336#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5337#define CAN_F12R2_FB23_Pos (23U)
5338#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5339#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5340#define CAN_F12R2_FB24_Pos (24U)
5341#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5342#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5343#define CAN_F12R2_FB25_Pos (25U)
5344#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5345#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5346#define CAN_F12R2_FB26_Pos (26U)
5347#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5348#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5349#define CAN_F12R2_FB27_Pos (27U)
5350#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5351#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5352#define CAN_F12R2_FB28_Pos (28U)
5353#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5354#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5355#define CAN_F12R2_FB29_Pos (29U)
5356#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5357#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5358#define CAN_F12R2_FB30_Pos (30U)
5359#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5360#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5361#define CAN_F12R2_FB31_Pos (31U)
5362#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5363#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5364
5365/******************* Bit definition for CAN_F13R2 register ******************/
5366#define CAN_F13R2_FB0_Pos (0U)
5367#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5368#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5369#define CAN_F13R2_FB1_Pos (1U)
5370#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5371#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5372#define CAN_F13R2_FB2_Pos (2U)
5373#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5374#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5375#define CAN_F13R2_FB3_Pos (3U)
5376#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5377#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5378#define CAN_F13R2_FB4_Pos (4U)
5379#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5380#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5381#define CAN_F13R2_FB5_Pos (5U)
5382#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5383#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5384#define CAN_F13R2_FB6_Pos (6U)
5385#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5386#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5387#define CAN_F13R2_FB7_Pos (7U)
5388#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5389#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5390#define CAN_F13R2_FB8_Pos (8U)
5391#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5392#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5393#define CAN_F13R2_FB9_Pos (9U)
5394#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5395#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5396#define CAN_F13R2_FB10_Pos (10U)
5397#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5398#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5399#define CAN_F13R2_FB11_Pos (11U)
5400#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5401#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5402#define CAN_F13R2_FB12_Pos (12U)
5403#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5404#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5405#define CAN_F13R2_FB13_Pos (13U)
5406#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5407#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5408#define CAN_F13R2_FB14_Pos (14U)
5409#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5410#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5411#define CAN_F13R2_FB15_Pos (15U)
5412#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5413#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5414#define CAN_F13R2_FB16_Pos (16U)
5415#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5416#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5417#define CAN_F13R2_FB17_Pos (17U)
5418#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5419#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5420#define CAN_F13R2_FB18_Pos (18U)
5421#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5422#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5423#define CAN_F13R2_FB19_Pos (19U)
5424#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5425#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5426#define CAN_F13R2_FB20_Pos (20U)
5427#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5428#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5429#define CAN_F13R2_FB21_Pos (21U)
5430#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5431#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5432#define CAN_F13R2_FB22_Pos (22U)
5433#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5434#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5435#define CAN_F13R2_FB23_Pos (23U)
5436#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5437#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5438#define CAN_F13R2_FB24_Pos (24U)
5439#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5440#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5441#define CAN_F13R2_FB25_Pos (25U)
5442#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5443#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5444#define CAN_F13R2_FB26_Pos (26U)
5445#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5446#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5447#define CAN_F13R2_FB27_Pos (27U)
5448#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5449#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5450#define CAN_F13R2_FB28_Pos (28U)
5451#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5452#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5453#define CAN_F13R2_FB29_Pos (29U)
5454#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5455#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5456#define CAN_F13R2_FB30_Pos (30U)
5457#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5458#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5459#define CAN_F13R2_FB31_Pos (31U)
5460#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5461#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5462
5463/******************************************************************************/
5464/* */
5465/* CRC calculation unit */
5466/* */
5467/******************************************************************************/
5468/******************* Bit definition for CRC_DR register *********************/
5469#define CRC_DR_DR_Pos (0U)
5470#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5471#define CRC_DR_DR CRC_DR_DR_Msk
5472
5473
5474/******************* Bit definition for CRC_IDR register ********************/
5475#define CRC_IDR_IDR_Pos (0U)
5476#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5477#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5478
5479
5480/******************** Bit definition for CRC_CR register ********************/
5481#define CRC_CR_RESET_Pos (0U)
5482#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5483#define CRC_CR_RESET CRC_CR_RESET_Msk
5484
5485/******************************************************************************/
5486/* */
5487/* Digital to Analog Converter */
5488/* */
5489/******************************************************************************/
5490/*
5491 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
5492 */
5493#define DAC_CHANNEL2_SUPPORT
5494/******************** Bit definition for DAC_CR register ********************/
5495#define DAC_CR_EN1_Pos (0U)
5496#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5497#define DAC_CR_EN1 DAC_CR_EN1_Msk
5498#define DAC_CR_BOFF1_Pos (1U)
5499#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
5500#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
5501#define DAC_CR_TEN1_Pos (2U)
5502#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5503#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5504
5505#define DAC_CR_TSEL1_Pos (3U)
5506#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
5507#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5508#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5509#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5510#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5511
5512#define DAC_CR_WAVE1_Pos (6U)
5513#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5514#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5515#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5516#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5517
5518#define DAC_CR_MAMP1_Pos (8U)
5519#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5520#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5521#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5522#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5523#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5524#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5525
5526#define DAC_CR_DMAEN1_Pos (12U)
5527#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5528#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5529#define DAC_CR_DMAUDRIE1_Pos (13U)
5530#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5531#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5532#define DAC_CR_EN2_Pos (16U)
5533#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5534#define DAC_CR_EN2 DAC_CR_EN2_Msk
5535#define DAC_CR_BOFF2_Pos (17U)
5536#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
5537#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
5538#define DAC_CR_TEN2_Pos (18U)
5539#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5540#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5541
5542#define DAC_CR_TSEL2_Pos (19U)
5543#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
5544#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5545#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5546#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5547#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5548
5549#define DAC_CR_WAVE2_Pos (22U)
5550#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5551#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5552#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5553#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5554
5555#define DAC_CR_MAMP2_Pos (24U)
5556#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5557#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5558#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5559#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5560#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5561#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5562
5563#define DAC_CR_DMAEN2_Pos (28U)
5564#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5565#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5566#define DAC_CR_DMAUDRIE2_Pos (29U)
5567#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5568#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5569
5570/***************** Bit definition for DAC_SWTRIGR register ******************/
5571#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5572#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5573#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5574#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5575#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5576#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5577
5578/***************** Bit definition for DAC_DHR12R1 register ******************/
5579#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5580#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5581#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5582
5583/***************** Bit definition for DAC_DHR12L1 register ******************/
5584#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5585#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5586#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5587
5588/****************** Bit definition for DAC_DHR8R1 register ******************/
5589#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5590#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5591#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5592
5593/***************** Bit definition for DAC_DHR12R2 register ******************/
5594#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5595#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5596#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5597
5598/***************** Bit definition for DAC_DHR12L2 register ******************/
5599#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5600#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5601#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5602
5603/****************** Bit definition for DAC_DHR8R2 register ******************/
5604#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5605#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5606#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5607
5608/***************** Bit definition for DAC_DHR12RD register ******************/
5609#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5610#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5611#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5612#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5613#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5614#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5615
5616/***************** Bit definition for DAC_DHR12LD register ******************/
5617#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5618#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5619#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5620#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5621#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5622#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5623
5624/****************** Bit definition for DAC_DHR8RD register ******************/
5625#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5626#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5627#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5628#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5629#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5630#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5631
5632/******************* Bit definition for DAC_DOR1 register *******************/
5633#define DAC_DOR1_DACC1DOR_Pos (0U)
5634#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5635#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5636
5637/******************* Bit definition for DAC_DOR2 register *******************/
5638#define DAC_DOR2_DACC2DOR_Pos (0U)
5639#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
5640#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
5641
5642/******************** Bit definition for DAC_SR register ********************/
5643#define DAC_SR_DMAUDR1_Pos (13U)
5644#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
5645#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
5646#define DAC_SR_DMAUDR2_Pos (29U)
5647#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
5648#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
5649
5650/******************************************************************************/
5651/* */
5652/* Digital Filter for Sigma Delta Modulators */
5653/* */
5654/******************************************************************************/
5655
5656/**************** DFSDM channel configuration registers ********************/
5657
5658/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
5659#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
5660#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)
5661#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk
5662#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
5663#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)
5664#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk
5665#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
5666#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)
5667#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk
5668#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
5669#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)
5670#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk
5671#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)
5672#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)
5673#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
5674#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)
5675#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk
5676#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)
5677#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)
5678#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
5679#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)
5680#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk
5681#define DFSDM_CHCFGR1_CHEN_Pos (7U)
5682#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)
5683#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk
5684#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
5685#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)
5686#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk
5687#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
5688#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)
5689#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk
5690#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
5691#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
5692#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk
5693#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
5694#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
5695#define DFSDM_CHCFGR1_SITP_Pos (0U)
5696#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos)
5697#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk
5698#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos)
5699#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos)
5700
5701/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
5702#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
5703#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)
5704#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk
5705#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
5706#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)
5707#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk
5708
5709/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
5710#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
5711#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)
5712#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk
5713#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)
5714#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)
5715#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
5716#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)
5717#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk
5718#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
5719#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)
5720#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk
5721#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
5722#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)
5723#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk
5724
5725/**************** Bit definition for DFSDM_CHWDATR register *******************/
5726#define DFSDM_CHWDATR_WDATA_Pos (0U)
5727#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)
5728#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk
5729
5730/**************** Bit definition for DFSDM_CHDATINR register *****************/
5731#define DFSDM_CHDATINR_INDAT0_Pos (0U)
5732#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)
5733#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk
5734#define DFSDM_CHDATINR_INDAT1_Pos (16U)
5735#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)
5736#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk
5737
5738/************************ DFSDM module registers ****************************/
5739
5740/***************** Bit definition for DFSDM_FLTCR1 register *******************/
5741#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
5742#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)
5743#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk
5744#define DFSDM_FLTCR1_FAST_Pos (29U)
5745#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos)
5746#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk
5747#define DFSDM_FLTCR1_RCH_Pos (24U)
5748#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos)
5749#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk
5750#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
5751#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)
5752#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk
5753#define DFSDM_FLTCR1_RSYNC_Pos (19U)
5754#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)
5755#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk
5756#define DFSDM_FLTCR1_RCONT_Pos (18U)
5757#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos)
5758#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk
5759#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
5760#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)
5761#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk
5762#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
5763#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)
5764#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk
5765#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)
5766#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)
5767#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
5768#define DFSDM_FLTCR1_JEXTSEL_Msk (0x7UL << DFSDM_FLTCR1_JEXTSEL_Pos)
5769#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk
5770#define DFSDM_FLTCR1_JEXTSEL_2 (0x4UL << DFSDM_FLTCR1_JEXTSEL_Pos)
5771#define DFSDM_FLTCR1_JEXTSEL_1 (0x2UL << DFSDM_FLTCR1_JEXTSEL_Pos)
5772#define DFSDM_FLTCR1_JEXTSEL_0 (0x1UL << DFSDM_FLTCR1_JEXTSEL_Pos)
5773#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
5774#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)
5775#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk
5776#define DFSDM_FLTCR1_JSCAN_Pos (4U)
5777#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)
5778#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk
5779#define DFSDM_FLTCR1_JSYNC_Pos (3U)
5780#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)
5781#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk
5782#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
5783#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)
5784#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk
5785#define DFSDM_FLTCR1_DFEN_Pos (0U)
5786#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos)
5787#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk
5788
5789/***************** Bit definition for DFSDM_FLTCR2 register *******************/
5790#define DFSDM_FLTCR2_AWDCH_Pos (16U)
5791#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)
5792#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk
5793#define DFSDM_FLTCR2_EXCH_Pos (8U)
5794#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)
5795#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk
5796#define DFSDM_FLTCR2_CKABIE_Pos (6U)
5797#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)
5798#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk
5799#define DFSDM_FLTCR2_SCDIE_Pos (5U)
5800#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)
5801#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk
5802#define DFSDM_FLTCR2_AWDIE_Pos (4U)
5803#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)
5804#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk
5805#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
5806#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)
5807#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk
5808#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
5809#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)
5810#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk
5811#define DFSDM_FLTCR2_REOCIE_Pos (1U)
5812#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)
5813#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk
5814#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
5815#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)
5816#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk
5817
5818/***************** Bit definition for DFSDM_FLTISR register *******************/
5819#define DFSDM_FLTISR_SCDF_Pos (24U)
5820#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos)
5821#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk
5822#define DFSDM_FLTISR_CKABF_Pos (16U)
5823#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos)
5824#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk
5825#define DFSDM_FLTISR_RCIP_Pos (14U)
5826#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos)
5827#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk
5828#define DFSDM_FLTISR_JCIP_Pos (13U)
5829#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos)
5830#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk
5831#define DFSDM_FLTISR_AWDF_Pos (4U)
5832#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos)
5833#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk
5834#define DFSDM_FLTISR_ROVRF_Pos (3U)
5835#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos)
5836#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk
5837#define DFSDM_FLTISR_JOVRF_Pos (2U)
5838#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos)
5839#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk
5840#define DFSDM_FLTISR_REOCF_Pos (1U)
5841#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos)
5842#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk
5843#define DFSDM_FLTISR_JEOCF_Pos (0U)
5844#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos)
5845#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk
5846
5847/***************** Bit definition for DFSDM_FLTICR register *******************/
5848#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
5849#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)
5850#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk
5851#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
5852#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)
5853#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk
5854#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
5855#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)
5856#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk
5857#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
5858#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)
5859#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk
5860
5861/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
5862#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
5863#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)
5864#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk
5865
5866/***************** Bit definition for DFSDM_FLTFCR register *******************/
5867#define DFSDM_FLTFCR_FORD_Pos (29U)
5868#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos)
5869#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk
5870#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos)
5871#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos)
5872#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos)
5873#define DFSDM_FLTFCR_FOSR_Pos (16U)
5874#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)
5875#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk
5876#define DFSDM_FLTFCR_IOSR_Pos (0U)
5877#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)
5878#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk
5879
5880/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
5881#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
5882#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)
5883#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk
5884#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
5885#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)
5886#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk
5887
5888/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
5889#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
5890#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)
5891#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk
5892#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
5893#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)
5894#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk
5895#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
5896#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)
5897#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk
5898
5899/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
5900#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
5901#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)
5902#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk
5903#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
5904#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)
5905#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk
5906
5907/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
5908#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
5909#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)
5910#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk
5911#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
5912#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)
5913#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk
5914
5915/*************** Bit definition for DFSDM_FLTAWSR register *******************/
5916#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
5917#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)
5918#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk
5919#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
5920#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)
5921#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk
5922
5923
5924/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
5925#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
5926#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)
5927#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk
5928#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
5929#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)
5930#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk
5931
5932/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
5933#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
5934#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)
5935#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk
5936#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
5937#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)
5938#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk
5939
5940/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
5941#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
5942#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)
5943#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk
5944#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
5945#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)
5946#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk
5947
5948/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
5949#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
5950#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)
5951#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk
5952
5953/* Legacy Defines */
5954#define DFSDM_FLTICR_CLRSCSDF_Pos DFSDM_FLTICR_CLRSCDF_Pos
5955#define DFSDM_FLTICR_CLRSCSDF_Msk DFSDM_FLTICR_CLRSCDF_Msk
5956#define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCDF
5957
5958/******************************************************************************/
5959/* */
5960/* DMA Controller */
5961/* */
5962/******************************************************************************/
5963/******************** Bits definition for DMA_SxCR register *****************/
5964#define DMA_SxCR_CHSEL_Pos (25U)
5965#define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos)
5966#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5967#define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos)
5968#define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos)
5969#define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos)
5970#define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos)
5971#define DMA_SxCR_MBURST_Pos (23U)
5972#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
5973#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5974#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
5975#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
5976#define DMA_SxCR_PBURST_Pos (21U)
5977#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
5978#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
5979#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
5980#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
5981#define DMA_SxCR_CT_Pos (19U)
5982#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
5983#define DMA_SxCR_CT DMA_SxCR_CT_Msk
5984#define DMA_SxCR_DBM_Pos (18U)
5985#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
5986#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
5987#define DMA_SxCR_PL_Pos (16U)
5988#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
5989#define DMA_SxCR_PL DMA_SxCR_PL_Msk
5990#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
5991#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
5992#define DMA_SxCR_PINCOS_Pos (15U)
5993#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
5994#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
5995#define DMA_SxCR_MSIZE_Pos (13U)
5996#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
5997#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
5998#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
5999#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
6000#define DMA_SxCR_PSIZE_Pos (11U)
6001#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
6002#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6003#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
6004#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
6005#define DMA_SxCR_MINC_Pos (10U)
6006#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
6007#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6008#define DMA_SxCR_PINC_Pos (9U)
6009#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
6010#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6011#define DMA_SxCR_CIRC_Pos (8U)
6012#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
6013#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6014#define DMA_SxCR_DIR_Pos (6U)
6015#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
6016#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6017#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
6018#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
6019#define DMA_SxCR_PFCTRL_Pos (5U)
6020#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
6021#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6022#define DMA_SxCR_TCIE_Pos (4U)
6023#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
6024#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6025#define DMA_SxCR_HTIE_Pos (3U)
6026#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
6027#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6028#define DMA_SxCR_TEIE_Pos (2U)
6029#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
6030#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6031#define DMA_SxCR_DMEIE_Pos (1U)
6032#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
6033#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6034#define DMA_SxCR_EN_Pos (0U)
6035#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
6036#define DMA_SxCR_EN DMA_SxCR_EN_Msk
6037
6038/* Legacy defines */
6039#define DMA_SxCR_ACK_Pos (20U)
6040#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)
6041#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
6042
6043/******************** Bits definition for DMA_SxCNDTR register **************/
6044#define DMA_SxNDT_Pos (0U)
6045#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
6046#define DMA_SxNDT DMA_SxNDT_Msk
6047#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
6048#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
6049#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
6050#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
6051#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
6052#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
6053#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
6054#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
6055#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
6056#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
6057#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
6058#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
6059#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
6060#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
6061#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
6062#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
6063
6064/******************** Bits definition for DMA_SxFCR register ****************/
6065#define DMA_SxFCR_FEIE_Pos (7U)
6066#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
6067#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6068#define DMA_SxFCR_FS_Pos (3U)
6069#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
6070#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6071#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
6072#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
6073#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
6074#define DMA_SxFCR_DMDIS_Pos (2U)
6075#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
6076#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6077#define DMA_SxFCR_FTH_Pos (0U)
6078#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
6079#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6080#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
6081#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
6082
6083/******************** Bits definition for DMA_LISR register *****************/
6084#define DMA_LISR_TCIF3_Pos (27U)
6085#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
6086#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6087#define DMA_LISR_HTIF3_Pos (26U)
6088#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
6089#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6090#define DMA_LISR_TEIF3_Pos (25U)
6091#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
6092#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6093#define DMA_LISR_DMEIF3_Pos (24U)
6094#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
6095#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6096#define DMA_LISR_FEIF3_Pos (22U)
6097#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
6098#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6099#define DMA_LISR_TCIF2_Pos (21U)
6100#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
6101#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6102#define DMA_LISR_HTIF2_Pos (20U)
6103#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
6104#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6105#define DMA_LISR_TEIF2_Pos (19U)
6106#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
6107#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6108#define DMA_LISR_DMEIF2_Pos (18U)
6109#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
6110#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6111#define DMA_LISR_FEIF2_Pos (16U)
6112#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
6113#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6114#define DMA_LISR_TCIF1_Pos (11U)
6115#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
6116#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6117#define DMA_LISR_HTIF1_Pos (10U)
6118#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
6119#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6120#define DMA_LISR_TEIF1_Pos (9U)
6121#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
6122#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6123#define DMA_LISR_DMEIF1_Pos (8U)
6124#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
6125#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6126#define DMA_LISR_FEIF1_Pos (6U)
6127#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
6128#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6129#define DMA_LISR_TCIF0_Pos (5U)
6130#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
6131#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6132#define DMA_LISR_HTIF0_Pos (4U)
6133#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
6134#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6135#define DMA_LISR_TEIF0_Pos (3U)
6136#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
6137#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6138#define DMA_LISR_DMEIF0_Pos (2U)
6139#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
6140#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6141#define DMA_LISR_FEIF0_Pos (0U)
6142#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
6143#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6144
6145/******************** Bits definition for DMA_HISR register *****************/
6146#define DMA_HISR_TCIF7_Pos (27U)
6147#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
6148#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6149#define DMA_HISR_HTIF7_Pos (26U)
6150#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
6151#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6152#define DMA_HISR_TEIF7_Pos (25U)
6153#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
6154#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6155#define DMA_HISR_DMEIF7_Pos (24U)
6156#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
6157#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6158#define DMA_HISR_FEIF7_Pos (22U)
6159#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
6160#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6161#define DMA_HISR_TCIF6_Pos (21U)
6162#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
6163#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6164#define DMA_HISR_HTIF6_Pos (20U)
6165#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
6166#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6167#define DMA_HISR_TEIF6_Pos (19U)
6168#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
6169#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6170#define DMA_HISR_DMEIF6_Pos (18U)
6171#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
6172#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6173#define DMA_HISR_FEIF6_Pos (16U)
6174#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
6175#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6176#define DMA_HISR_TCIF5_Pos (11U)
6177#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
6178#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6179#define DMA_HISR_HTIF5_Pos (10U)
6180#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
6181#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6182#define DMA_HISR_TEIF5_Pos (9U)
6183#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
6184#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6185#define DMA_HISR_DMEIF5_Pos (8U)
6186#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
6187#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6188#define DMA_HISR_FEIF5_Pos (6U)
6189#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
6190#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6191#define DMA_HISR_TCIF4_Pos (5U)
6192#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
6193#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6194#define DMA_HISR_HTIF4_Pos (4U)
6195#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
6196#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6197#define DMA_HISR_TEIF4_Pos (3U)
6198#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
6199#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6200#define DMA_HISR_DMEIF4_Pos (2U)
6201#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
6202#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6203#define DMA_HISR_FEIF4_Pos (0U)
6204#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
6205#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6206
6207/******************** Bits definition for DMA_LIFCR register ****************/
6208#define DMA_LIFCR_CTCIF3_Pos (27U)
6209#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
6210#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6211#define DMA_LIFCR_CHTIF3_Pos (26U)
6212#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
6213#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6214#define DMA_LIFCR_CTEIF3_Pos (25U)
6215#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
6216#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6217#define DMA_LIFCR_CDMEIF3_Pos (24U)
6218#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
6219#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6220#define DMA_LIFCR_CFEIF3_Pos (22U)
6221#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
6222#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6223#define DMA_LIFCR_CTCIF2_Pos (21U)
6224#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
6225#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6226#define DMA_LIFCR_CHTIF2_Pos (20U)
6227#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
6228#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6229#define DMA_LIFCR_CTEIF2_Pos (19U)
6230#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
6231#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6232#define DMA_LIFCR_CDMEIF2_Pos (18U)
6233#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
6234#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6235#define DMA_LIFCR_CFEIF2_Pos (16U)
6236#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
6237#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6238#define DMA_LIFCR_CTCIF1_Pos (11U)
6239#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
6240#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6241#define DMA_LIFCR_CHTIF1_Pos (10U)
6242#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
6243#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6244#define DMA_LIFCR_CTEIF1_Pos (9U)
6245#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
6246#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6247#define DMA_LIFCR_CDMEIF1_Pos (8U)
6248#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
6249#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6250#define DMA_LIFCR_CFEIF1_Pos (6U)
6251#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
6252#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6253#define DMA_LIFCR_CTCIF0_Pos (5U)
6254#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
6255#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6256#define DMA_LIFCR_CHTIF0_Pos (4U)
6257#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
6258#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6259#define DMA_LIFCR_CTEIF0_Pos (3U)
6260#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
6261#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6262#define DMA_LIFCR_CDMEIF0_Pos (2U)
6263#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
6264#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6265#define DMA_LIFCR_CFEIF0_Pos (0U)
6266#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
6267#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6268
6269/******************** Bits definition for DMA_HIFCR register ****************/
6270#define DMA_HIFCR_CTCIF7_Pos (27U)
6271#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
6272#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6273#define DMA_HIFCR_CHTIF7_Pos (26U)
6274#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
6275#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6276#define DMA_HIFCR_CTEIF7_Pos (25U)
6277#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
6278#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6279#define DMA_HIFCR_CDMEIF7_Pos (24U)
6280#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
6281#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6282#define DMA_HIFCR_CFEIF7_Pos (22U)
6283#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
6284#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6285#define DMA_HIFCR_CTCIF6_Pos (21U)
6286#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
6287#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6288#define DMA_HIFCR_CHTIF6_Pos (20U)
6289#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
6290#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6291#define DMA_HIFCR_CTEIF6_Pos (19U)
6292#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
6293#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6294#define DMA_HIFCR_CDMEIF6_Pos (18U)
6295#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
6296#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6297#define DMA_HIFCR_CFEIF6_Pos (16U)
6298#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
6299#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6300#define DMA_HIFCR_CTCIF5_Pos (11U)
6301#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
6302#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6303#define DMA_HIFCR_CHTIF5_Pos (10U)
6304#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
6305#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6306#define DMA_HIFCR_CTEIF5_Pos (9U)
6307#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
6308#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6309#define DMA_HIFCR_CDMEIF5_Pos (8U)
6310#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
6311#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6312#define DMA_HIFCR_CFEIF5_Pos (6U)
6313#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
6314#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6315#define DMA_HIFCR_CTCIF4_Pos (5U)
6316#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
6317#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6318#define DMA_HIFCR_CHTIF4_Pos (4U)
6319#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
6320#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6321#define DMA_HIFCR_CTEIF4_Pos (3U)
6322#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
6323#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6324#define DMA_HIFCR_CDMEIF4_Pos (2U)
6325#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
6326#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6327#define DMA_HIFCR_CFEIF4_Pos (0U)
6328#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
6329#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6330
6331/****************** Bit definition for DMA_SxPAR register ********************/
6332#define DMA_SxPAR_PA_Pos (0U)
6333#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
6334#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
6335
6336/****************** Bit definition for DMA_SxM0AR register ********************/
6337#define DMA_SxM0AR_M0A_Pos (0U)
6338#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
6339#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
6340
6341/****************** Bit definition for DMA_SxM1AR register ********************/
6342#define DMA_SxM1AR_M1A_Pos (0U)
6343#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
6344#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
6345
6346
6347/******************************************************************************/
6348/* */
6349/* External Interrupt/Event Controller */
6350/* */
6351/******************************************************************************/
6352/******************* Bit definition for EXTI_IMR register *******************/
6353#define EXTI_IMR_MR0_Pos (0U)
6354#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
6355#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
6356#define EXTI_IMR_MR1_Pos (1U)
6357#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
6358#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
6359#define EXTI_IMR_MR2_Pos (2U)
6360#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
6361#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
6362#define EXTI_IMR_MR3_Pos (3U)
6363#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
6364#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
6365#define EXTI_IMR_MR4_Pos (4U)
6366#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
6367#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
6368#define EXTI_IMR_MR5_Pos (5U)
6369#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
6370#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
6371#define EXTI_IMR_MR6_Pos (6U)
6372#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
6373#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
6374#define EXTI_IMR_MR7_Pos (7U)
6375#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
6376#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
6377#define EXTI_IMR_MR8_Pos (8U)
6378#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
6379#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
6380#define EXTI_IMR_MR9_Pos (9U)
6381#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
6382#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
6383#define EXTI_IMR_MR10_Pos (10U)
6384#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
6385#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
6386#define EXTI_IMR_MR11_Pos (11U)
6387#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
6388#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
6389#define EXTI_IMR_MR12_Pos (12U)
6390#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
6391#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
6392#define EXTI_IMR_MR13_Pos (13U)
6393#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
6394#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
6395#define EXTI_IMR_MR14_Pos (14U)
6396#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
6397#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
6398#define EXTI_IMR_MR15_Pos (15U)
6399#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
6400#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
6401#define EXTI_IMR_MR16_Pos (16U)
6402#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
6403#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
6404#define EXTI_IMR_MR17_Pos (17U)
6405#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
6406#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
6407#define EXTI_IMR_MR18_Pos (18U)
6408#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
6409#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
6410#define EXTI_IMR_MR19_Pos (19U)
6411#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
6412#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
6413#define EXTI_IMR_MR20_Pos (20U)
6414#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
6415#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
6416#define EXTI_IMR_MR21_Pos (21U)
6417#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
6418#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
6419#define EXTI_IMR_MR22_Pos (22U)
6420#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
6421#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
6422#define EXTI_IMR_MR23_Pos (23U)
6423#define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos)
6424#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk
6425
6426/* Reference Defines */
6427#define EXTI_IMR_IM0 EXTI_IMR_MR0
6428#define EXTI_IMR_IM1 EXTI_IMR_MR1
6429#define EXTI_IMR_IM2 EXTI_IMR_MR2
6430#define EXTI_IMR_IM3 EXTI_IMR_MR3
6431#define EXTI_IMR_IM4 EXTI_IMR_MR4
6432#define EXTI_IMR_IM5 EXTI_IMR_MR5
6433#define EXTI_IMR_IM6 EXTI_IMR_MR6
6434#define EXTI_IMR_IM7 EXTI_IMR_MR7
6435#define EXTI_IMR_IM8 EXTI_IMR_MR8
6436#define EXTI_IMR_IM9 EXTI_IMR_MR9
6437#define EXTI_IMR_IM10 EXTI_IMR_MR10
6438#define EXTI_IMR_IM11 EXTI_IMR_MR11
6439#define EXTI_IMR_IM12 EXTI_IMR_MR12
6440#define EXTI_IMR_IM13 EXTI_IMR_MR13
6441#define EXTI_IMR_IM14 EXTI_IMR_MR14
6442#define EXTI_IMR_IM15 EXTI_IMR_MR15
6443#define EXTI_IMR_IM16 EXTI_IMR_MR16
6444#define EXTI_IMR_IM17 EXTI_IMR_MR17
6445#define EXTI_IMR_IM18 EXTI_IMR_MR18
6446#define EXTI_IMR_IM19 EXTI_IMR_MR19
6447#define EXTI_IMR_IM20 EXTI_IMR_MR20
6448#define EXTI_IMR_IM21 EXTI_IMR_MR21
6449#define EXTI_IMR_IM22 EXTI_IMR_MR22
6450#define EXTI_IMR_IM23 EXTI_IMR_MR23
6451#define EXTI_IMR_IM_Pos (0U)
6452#define EXTI_IMR_IM_Msk (0xFFFFFFUL << EXTI_IMR_IM_Pos)
6453#define EXTI_IMR_IM EXTI_IMR_IM_Msk
6454
6455/******************* Bit definition for EXTI_EMR register *******************/
6456#define EXTI_EMR_MR0_Pos (0U)
6457#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
6458#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
6459#define EXTI_EMR_MR1_Pos (1U)
6460#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
6461#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
6462#define EXTI_EMR_MR2_Pos (2U)
6463#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
6464#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
6465#define EXTI_EMR_MR3_Pos (3U)
6466#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
6467#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
6468#define EXTI_EMR_MR4_Pos (4U)
6469#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
6470#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
6471#define EXTI_EMR_MR5_Pos (5U)
6472#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
6473#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
6474#define EXTI_EMR_MR6_Pos (6U)
6475#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
6476#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
6477#define EXTI_EMR_MR7_Pos (7U)
6478#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
6479#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
6480#define EXTI_EMR_MR8_Pos (8U)
6481#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
6482#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
6483#define EXTI_EMR_MR9_Pos (9U)
6484#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
6485#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
6486#define EXTI_EMR_MR10_Pos (10U)
6487#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
6488#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
6489#define EXTI_EMR_MR11_Pos (11U)
6490#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
6491#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
6492#define EXTI_EMR_MR12_Pos (12U)
6493#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
6494#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
6495#define EXTI_EMR_MR13_Pos (13U)
6496#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
6497#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
6498#define EXTI_EMR_MR14_Pos (14U)
6499#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
6500#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
6501#define EXTI_EMR_MR15_Pos (15U)
6502#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
6503#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
6504#define EXTI_EMR_MR16_Pos (16U)
6505#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
6506#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
6507#define EXTI_EMR_MR17_Pos (17U)
6508#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
6509#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
6510#define EXTI_EMR_MR18_Pos (18U)
6511#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
6512#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
6513#define EXTI_EMR_MR19_Pos (19U)
6514#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
6515#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
6516#define EXTI_EMR_MR20_Pos (20U)
6517#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
6518#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
6519#define EXTI_EMR_MR21_Pos (21U)
6520#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
6521#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
6522#define EXTI_EMR_MR22_Pos (22U)
6523#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
6524#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
6525#define EXTI_EMR_MR23_Pos (23U)
6526#define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos)
6527#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk
6528
6529/* Reference Defines */
6530#define EXTI_EMR_EM0 EXTI_EMR_MR0
6531#define EXTI_EMR_EM1 EXTI_EMR_MR1
6532#define EXTI_EMR_EM2 EXTI_EMR_MR2
6533#define EXTI_EMR_EM3 EXTI_EMR_MR3
6534#define EXTI_EMR_EM4 EXTI_EMR_MR4
6535#define EXTI_EMR_EM5 EXTI_EMR_MR5
6536#define EXTI_EMR_EM6 EXTI_EMR_MR6
6537#define EXTI_EMR_EM7 EXTI_EMR_MR7
6538#define EXTI_EMR_EM8 EXTI_EMR_MR8
6539#define EXTI_EMR_EM9 EXTI_EMR_MR9
6540#define EXTI_EMR_EM10 EXTI_EMR_MR10
6541#define EXTI_EMR_EM11 EXTI_EMR_MR11
6542#define EXTI_EMR_EM12 EXTI_EMR_MR12
6543#define EXTI_EMR_EM13 EXTI_EMR_MR13
6544#define EXTI_EMR_EM14 EXTI_EMR_MR14
6545#define EXTI_EMR_EM15 EXTI_EMR_MR15
6546#define EXTI_EMR_EM16 EXTI_EMR_MR16
6547#define EXTI_EMR_EM17 EXTI_EMR_MR17
6548#define EXTI_EMR_EM18 EXTI_EMR_MR18
6549#define EXTI_EMR_EM19 EXTI_EMR_MR19
6550#define EXTI_EMR_EM20 EXTI_EMR_MR20
6551#define EXTI_EMR_EM21 EXTI_EMR_MR21
6552#define EXTI_EMR_EM22 EXTI_EMR_MR22
6553#define EXTI_EMR_EM23 EXTI_EMR_MR23
6554
6555/****************** Bit definition for EXTI_RTSR register *******************/
6556#define EXTI_RTSR_TR0_Pos (0U)
6557#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
6558#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
6559#define EXTI_RTSR_TR1_Pos (1U)
6560#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
6561#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
6562#define EXTI_RTSR_TR2_Pos (2U)
6563#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
6564#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
6565#define EXTI_RTSR_TR3_Pos (3U)
6566#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
6567#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
6568#define EXTI_RTSR_TR4_Pos (4U)
6569#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
6570#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
6571#define EXTI_RTSR_TR5_Pos (5U)
6572#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
6573#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
6574#define EXTI_RTSR_TR6_Pos (6U)
6575#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
6576#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
6577#define EXTI_RTSR_TR7_Pos (7U)
6578#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
6579#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
6580#define EXTI_RTSR_TR8_Pos (8U)
6581#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
6582#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
6583#define EXTI_RTSR_TR9_Pos (9U)
6584#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
6585#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
6586#define EXTI_RTSR_TR10_Pos (10U)
6587#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
6588#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
6589#define EXTI_RTSR_TR11_Pos (11U)
6590#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
6591#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
6592#define EXTI_RTSR_TR12_Pos (12U)
6593#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
6594#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
6595#define EXTI_RTSR_TR13_Pos (13U)
6596#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
6597#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
6598#define EXTI_RTSR_TR14_Pos (14U)
6599#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
6600#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
6601#define EXTI_RTSR_TR15_Pos (15U)
6602#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
6603#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
6604#define EXTI_RTSR_TR16_Pos (16U)
6605#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
6606#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
6607#define EXTI_RTSR_TR17_Pos (17U)
6608#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
6609#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
6610#define EXTI_RTSR_TR18_Pos (18U)
6611#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
6612#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
6613#define EXTI_RTSR_TR19_Pos (19U)
6614#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
6615#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
6616#define EXTI_RTSR_TR20_Pos (20U)
6617#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
6618#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
6619#define EXTI_RTSR_TR21_Pos (21U)
6620#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
6621#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
6622#define EXTI_RTSR_TR22_Pos (22U)
6623#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
6624#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
6625#define EXTI_RTSR_TR23_Pos (23U)
6626#define EXTI_RTSR_TR23_Msk (0x1UL << EXTI_RTSR_TR23_Pos)
6627#define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk
6628
6629/****************** Bit definition for EXTI_FTSR register *******************/
6630#define EXTI_FTSR_TR0_Pos (0U)
6631#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
6632#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
6633#define EXTI_FTSR_TR1_Pos (1U)
6634#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
6635#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
6636#define EXTI_FTSR_TR2_Pos (2U)
6637#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
6638#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
6639#define EXTI_FTSR_TR3_Pos (3U)
6640#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
6641#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
6642#define EXTI_FTSR_TR4_Pos (4U)
6643#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
6644#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
6645#define EXTI_FTSR_TR5_Pos (5U)
6646#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
6647#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
6648#define EXTI_FTSR_TR6_Pos (6U)
6649#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
6650#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
6651#define EXTI_FTSR_TR7_Pos (7U)
6652#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
6653#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
6654#define EXTI_FTSR_TR8_Pos (8U)
6655#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
6656#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
6657#define EXTI_FTSR_TR9_Pos (9U)
6658#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
6659#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
6660#define EXTI_FTSR_TR10_Pos (10U)
6661#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
6662#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
6663#define EXTI_FTSR_TR11_Pos (11U)
6664#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
6665#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
6666#define EXTI_FTSR_TR12_Pos (12U)
6667#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
6668#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
6669#define EXTI_FTSR_TR13_Pos (13U)
6670#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
6671#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
6672#define EXTI_FTSR_TR14_Pos (14U)
6673#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
6674#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
6675#define EXTI_FTSR_TR15_Pos (15U)
6676#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
6677#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
6678#define EXTI_FTSR_TR16_Pos (16U)
6679#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
6680#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
6681#define EXTI_FTSR_TR17_Pos (17U)
6682#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
6683#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
6684#define EXTI_FTSR_TR18_Pos (18U)
6685#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
6686#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
6687#define EXTI_FTSR_TR19_Pos (19U)
6688#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
6689#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
6690#define EXTI_FTSR_TR20_Pos (20U)
6691#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
6692#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
6693#define EXTI_FTSR_TR21_Pos (21U)
6694#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
6695#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
6696#define EXTI_FTSR_TR22_Pos (22U)
6697#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
6698#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
6699#define EXTI_FTSR_TR23_Pos (23U)
6700#define EXTI_FTSR_TR23_Msk (0x1UL << EXTI_FTSR_TR23_Pos)
6701#define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk
6702
6703/****************** Bit definition for EXTI_SWIER register ******************/
6704#define EXTI_SWIER_SWIER0_Pos (0U)
6705#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
6706#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
6707#define EXTI_SWIER_SWIER1_Pos (1U)
6708#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
6709#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
6710#define EXTI_SWIER_SWIER2_Pos (2U)
6711#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
6712#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
6713#define EXTI_SWIER_SWIER3_Pos (3U)
6714#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
6715#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
6716#define EXTI_SWIER_SWIER4_Pos (4U)
6717#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
6718#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
6719#define EXTI_SWIER_SWIER5_Pos (5U)
6720#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
6721#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
6722#define EXTI_SWIER_SWIER6_Pos (6U)
6723#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
6724#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
6725#define EXTI_SWIER_SWIER7_Pos (7U)
6726#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
6727#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
6728#define EXTI_SWIER_SWIER8_Pos (8U)
6729#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
6730#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
6731#define EXTI_SWIER_SWIER9_Pos (9U)
6732#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
6733#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
6734#define EXTI_SWIER_SWIER10_Pos (10U)
6735#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
6736#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
6737#define EXTI_SWIER_SWIER11_Pos (11U)
6738#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
6739#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
6740#define EXTI_SWIER_SWIER12_Pos (12U)
6741#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
6742#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
6743#define EXTI_SWIER_SWIER13_Pos (13U)
6744#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
6745#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
6746#define EXTI_SWIER_SWIER14_Pos (14U)
6747#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
6748#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
6749#define EXTI_SWIER_SWIER15_Pos (15U)
6750#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
6751#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
6752#define EXTI_SWIER_SWIER16_Pos (16U)
6753#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
6754#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
6755#define EXTI_SWIER_SWIER17_Pos (17U)
6756#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
6757#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
6758#define EXTI_SWIER_SWIER18_Pos (18U)
6759#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
6760#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
6761#define EXTI_SWIER_SWIER19_Pos (19U)
6762#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
6763#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
6764#define EXTI_SWIER_SWIER20_Pos (20U)
6765#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
6766#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
6767#define EXTI_SWIER_SWIER21_Pos (21U)
6768#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
6769#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
6770#define EXTI_SWIER_SWIER22_Pos (22U)
6771#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
6772#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
6773#define EXTI_SWIER_SWIER23_Pos (23U)
6774#define EXTI_SWIER_SWIER23_Msk (0x1UL << EXTI_SWIER_SWIER23_Pos)
6775#define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk
6776
6777/******************* Bit definition for EXTI_PR register ********************/
6778#define EXTI_PR_PR0_Pos (0U)
6779#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
6780#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
6781#define EXTI_PR_PR1_Pos (1U)
6782#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
6783#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
6784#define EXTI_PR_PR2_Pos (2U)
6785#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
6786#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
6787#define EXTI_PR_PR3_Pos (3U)
6788#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
6789#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
6790#define EXTI_PR_PR4_Pos (4U)
6791#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
6792#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
6793#define EXTI_PR_PR5_Pos (5U)
6794#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
6795#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
6796#define EXTI_PR_PR6_Pos (6U)
6797#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
6798#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
6799#define EXTI_PR_PR7_Pos (7U)
6800#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
6801#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
6802#define EXTI_PR_PR8_Pos (8U)
6803#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
6804#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
6805#define EXTI_PR_PR9_Pos (9U)
6806#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
6807#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
6808#define EXTI_PR_PR10_Pos (10U)
6809#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
6810#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
6811#define EXTI_PR_PR11_Pos (11U)
6812#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
6813#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
6814#define EXTI_PR_PR12_Pos (12U)
6815#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
6816#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
6817#define EXTI_PR_PR13_Pos (13U)
6818#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
6819#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
6820#define EXTI_PR_PR14_Pos (14U)
6821#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
6822#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
6823#define EXTI_PR_PR15_Pos (15U)
6824#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
6825#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
6826#define EXTI_PR_PR16_Pos (16U)
6827#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
6828#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
6829#define EXTI_PR_PR17_Pos (17U)
6830#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
6831#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
6832#define EXTI_PR_PR18_Pos (18U)
6833#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
6834#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
6835#define EXTI_PR_PR19_Pos (19U)
6836#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
6837#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
6838#define EXTI_PR_PR20_Pos (20U)
6839#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
6840#define EXTI_PR_PR20 EXTI_PR_PR20_Msk
6841#define EXTI_PR_PR21_Pos (21U)
6842#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
6843#define EXTI_PR_PR21 EXTI_PR_PR21_Msk
6844#define EXTI_PR_PR22_Pos (22U)
6845#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
6846#define EXTI_PR_PR22 EXTI_PR_PR22_Msk
6847#define EXTI_PR_PR23_Pos (23U)
6848#define EXTI_PR_PR23_Msk (0x1UL << EXTI_PR_PR23_Pos)
6849#define EXTI_PR_PR23 EXTI_PR_PR23_Msk
6850
6851/******************************************************************************/
6852/* */
6853/* FLASH */
6854/* */
6855/******************************************************************************/
6856/******************* Bits definition for FLASH_ACR register *****************/
6857#define FLASH_ACR_LATENCY_Pos (0U)
6858#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)
6859#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6860#define FLASH_ACR_LATENCY_0WS 0x00000000U
6861#define FLASH_ACR_LATENCY_1WS 0x00000001U
6862#define FLASH_ACR_LATENCY_2WS 0x00000002U
6863#define FLASH_ACR_LATENCY_3WS 0x00000003U
6864#define FLASH_ACR_LATENCY_4WS 0x00000004U
6865#define FLASH_ACR_LATENCY_5WS 0x00000005U
6866#define FLASH_ACR_LATENCY_6WS 0x00000006U
6867#define FLASH_ACR_LATENCY_7WS 0x00000007U
6868
6869
6870#define FLASH_ACR_PRFTEN_Pos (8U)
6871#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
6872#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6873#define FLASH_ACR_ICEN_Pos (9U)
6874#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
6875#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
6876#define FLASH_ACR_DCEN_Pos (10U)
6877#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
6878#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
6879#define FLASH_ACR_ICRST_Pos (11U)
6880#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
6881#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
6882#define FLASH_ACR_DCRST_Pos (12U)
6883#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
6884#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
6885
6886/******************* Bits definition for FLASH_SR register ******************/
6887#define FLASH_SR_EOP_Pos (0U)
6888#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
6889#define FLASH_SR_EOP FLASH_SR_EOP_Msk
6890#define FLASH_SR_OPERR_Pos (1U)
6891#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
6892#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
6893#define FLASH_SR_WRPERR_Pos (4U)
6894#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
6895#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6896#define FLASH_SR_PGAERR_Pos (5U)
6897#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
6898#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6899#define FLASH_SR_PGPERR_Pos (6U)
6900#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
6901#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
6902#define FLASH_SR_PGSERR_Pos (7U)
6903#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
6904#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
6905#define FLASH_SR_RDERR_Pos (8U)
6906#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
6907#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
6908#define FLASH_SR_BSY_Pos (16U)
6909#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
6910#define FLASH_SR_BSY FLASH_SR_BSY_Msk
6911
6912/******************* Bits definition for FLASH_CR register ******************/
6913#define FLASH_CR_PG_Pos (0U)
6914#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
6915#define FLASH_CR_PG FLASH_CR_PG_Msk
6916#define FLASH_CR_SER_Pos (1U)
6917#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
6918#define FLASH_CR_SER FLASH_CR_SER_Msk
6919#define FLASH_CR_MER_Pos (2U)
6920#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
6921#define FLASH_CR_MER FLASH_CR_MER_Msk
6922#define FLASH_CR_SNB_Pos (3U)
6923#define FLASH_CR_SNB_Msk (0x0FUL << FLASH_CR_SNB_Pos)
6924#define FLASH_CR_SNB FLASH_CR_SNB_Msk
6925#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
6926#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
6927#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
6928#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
6929#define FLASH_CR_PSIZE_Pos (8U)
6930#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
6931#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
6932#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
6933#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
6934#define FLASH_CR_STRT_Pos (16U)
6935#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
6936#define FLASH_CR_STRT FLASH_CR_STRT_Msk
6937#define FLASH_CR_EOPIE_Pos (24U)
6938#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
6939#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6940#define FLASH_CR_ERRIE_Pos (25U)
6941#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
6942#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
6943#define FLASH_CR_LOCK_Pos (31U)
6944#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
6945#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6946
6947/******************* Bits definition for FLASH_OPTCR register ***************/
6948#define FLASH_OPTCR_OPTLOCK_Pos (0U)
6949#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
6950#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
6951#define FLASH_OPTCR_OPTSTRT_Pos (1U)
6952#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
6953#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
6954
6955#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
6956#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
6957#define FLASH_OPTCR_BOR_LEV_Pos (2U)
6958#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
6959#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
6960#define FLASH_OPTCR_WDG_SW_Pos (5U)
6961#define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
6962#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
6963#define FLASH_OPTCR_nRST_STOP_Pos (6U)
6964#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
6965#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
6966#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
6967#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
6968#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
6969#define FLASH_OPTCR_RDP_Pos (8U)
6970#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
6971#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
6972#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
6973#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
6974#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
6975#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
6976#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
6977#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
6978#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
6979#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
6980#define FLASH_OPTCR_nWRP_Pos (16U)
6981#define FLASH_OPTCR_nWRP_Msk (0x7FFFUL << FLASH_OPTCR_nWRP_Pos)
6982#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
6983#define FLASH_OPTCR_nWRP_0 0x00010000U
6984#define FLASH_OPTCR_nWRP_1 0x00020000U
6985#define FLASH_OPTCR_nWRP_2 0x00040000U
6986#define FLASH_OPTCR_nWRP_3 0x00080000U
6987#define FLASH_OPTCR_nWRP_4 0x00100000U
6988#define FLASH_OPTCR_nWRP_5 0x00200000U
6989#define FLASH_OPTCR_nWRP_6 0x00400000U
6990#define FLASH_OPTCR_nWRP_7 0x00800000U
6991#define FLASH_OPTCR_nWRP_8 0x01000000U
6992#define FLASH_OPTCR_nWRP_9 0x02000000U
6993#define FLASH_OPTCR_nWRP_10 0x04000000U
6994#define FLASH_OPTCR_nWRP_11 0x08000000U
6995#define FLASH_OPTCR_nWRP_12 0x10000000U
6996#define FLASH_OPTCR_nWRP_13 0x20000000U
6997#define FLASH_OPTCR_nWRP_14 0x40000000U
6998#define FLASH_OPTCR_nWRP_15 0x40000000U
6999
7000/****************** Bits definition for FLASH_OPTCR1 register ***************/
7001#define FLASH_OPTCR1_nWRP_Pos (16U)
7002#define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
7003#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
7004#define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos)
7005#define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos)
7006#define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos)
7007#define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos)
7008#define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos)
7009#define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos)
7010#define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos)
7011#define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos)
7012#define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos)
7013#define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos)
7014#define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos)
7015#define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos)
7016/* Legacy defines */
7017#define FLASH_SR_SOP_Pos FLASH_SR_OPERR_Pos
7018#define FLASH_SR_SOP_Msk FLASH_SR_OPERR_Msk
7019#define FLASH_SR_SOP FLASH_SR_OPERR
7020#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
7021#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
7022#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
7023#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
7024#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
7025#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
7026
7027/******************************************************************************/
7028/* */
7029/* Flexible Static Memory Controller */
7030/* */
7031/******************************************************************************/
7032/****************** Bit definition for FSMC_BCR1 register *******************/
7033#define FSMC_BCR1_MBKEN_Pos (0U)
7034#define FSMC_BCR1_MBKEN_Msk (0x1UL << FSMC_BCR1_MBKEN_Pos)
7035#define FSMC_BCR1_MBKEN FSMC_BCR1_MBKEN_Msk
7036#define FSMC_BCR1_MUXEN_Pos (1U)
7037#define FSMC_BCR1_MUXEN_Msk (0x1UL << FSMC_BCR1_MUXEN_Pos)
7038#define FSMC_BCR1_MUXEN FSMC_BCR1_MUXEN_Msk
7039
7040#define FSMC_BCR1_MTYP_Pos (2U)
7041#define FSMC_BCR1_MTYP_Msk (0x3UL << FSMC_BCR1_MTYP_Pos)
7042#define FSMC_BCR1_MTYP FSMC_BCR1_MTYP_Msk
7043#define FSMC_BCR1_MTYP_0 (0x1UL << FSMC_BCR1_MTYP_Pos)
7044#define FSMC_BCR1_MTYP_1 (0x2UL << FSMC_BCR1_MTYP_Pos)
7045
7046#define FSMC_BCR1_MWID_Pos (4U)
7047#define FSMC_BCR1_MWID_Msk (0x3UL << FSMC_BCR1_MWID_Pos)
7048#define FSMC_BCR1_MWID FSMC_BCR1_MWID_Msk
7049#define FSMC_BCR1_MWID_0 (0x1UL << FSMC_BCR1_MWID_Pos)
7050#define FSMC_BCR1_MWID_1 (0x2UL << FSMC_BCR1_MWID_Pos)
7051
7052#define FSMC_BCR1_FACCEN_Pos (6U)
7053#define FSMC_BCR1_FACCEN_Msk (0x1UL << FSMC_BCR1_FACCEN_Pos)
7054#define FSMC_BCR1_FACCEN FSMC_BCR1_FACCEN_Msk
7055#define FSMC_BCR1_BURSTEN_Pos (8U)
7056#define FSMC_BCR1_BURSTEN_Msk (0x1UL << FSMC_BCR1_BURSTEN_Pos)
7057#define FSMC_BCR1_BURSTEN FSMC_BCR1_BURSTEN_Msk
7058#define FSMC_BCR1_WAITPOL_Pos (9U)
7059#define FSMC_BCR1_WAITPOL_Msk (0x1UL << FSMC_BCR1_WAITPOL_Pos)
7060#define FSMC_BCR1_WAITPOL FSMC_BCR1_WAITPOL_Msk
7061#define FSMC_BCR1_WAITCFG_Pos (11U)
7062#define FSMC_BCR1_WAITCFG_Msk (0x1UL << FSMC_BCR1_WAITCFG_Pos)
7063#define FSMC_BCR1_WAITCFG FSMC_BCR1_WAITCFG_Msk
7064#define FSMC_BCR1_WREN_Pos (12U)
7065#define FSMC_BCR1_WREN_Msk (0x1UL << FSMC_BCR1_WREN_Pos)
7066#define FSMC_BCR1_WREN FSMC_BCR1_WREN_Msk
7067#define FSMC_BCR1_WAITEN_Pos (13U)
7068#define FSMC_BCR1_WAITEN_Msk (0x1UL << FSMC_BCR1_WAITEN_Pos)
7069#define FSMC_BCR1_WAITEN FSMC_BCR1_WAITEN_Msk
7070#define FSMC_BCR1_EXTMOD_Pos (14U)
7071#define FSMC_BCR1_EXTMOD_Msk (0x1UL << FSMC_BCR1_EXTMOD_Pos)
7072#define FSMC_BCR1_EXTMOD FSMC_BCR1_EXTMOD_Msk
7073#define FSMC_BCR1_ASYNCWAIT_Pos (15U)
7074#define FSMC_BCR1_ASYNCWAIT_Msk (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)
7075#define FSMC_BCR1_ASYNCWAIT FSMC_BCR1_ASYNCWAIT_Msk
7076#define FSMC_BCR1_CPSIZE_Pos (16U)
7077#define FSMC_BCR1_CPSIZE_Msk (0x7UL << FSMC_BCR1_CPSIZE_Pos)
7078#define FSMC_BCR1_CPSIZE FSMC_BCR1_CPSIZE_Msk
7079#define FSMC_BCR1_CPSIZE_0 (0x1UL << FSMC_BCR1_CPSIZE_Pos)
7080#define FSMC_BCR1_CPSIZE_1 (0x2UL << FSMC_BCR1_CPSIZE_Pos)
7081#define FSMC_BCR1_CPSIZE_2 (0x4UL << FSMC_BCR1_CPSIZE_Pos)
7082#define FSMC_BCR1_CBURSTRW_Pos (19U)
7083#define FSMC_BCR1_CBURSTRW_Msk (0x1UL << FSMC_BCR1_CBURSTRW_Pos)
7084#define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk
7085#define FSMC_BCR1_CCLKEN_Pos (20U)
7086#define FSMC_BCR1_CCLKEN_Msk (0x1UL << FSMC_BCR1_CCLKEN_Pos)
7087#define FSMC_BCR1_CCLKEN FSMC_BCR1_CCLKEN_Msk
7088#define FSMC_BCR1_WFDIS_Pos (21U)
7089#define FSMC_BCR1_WFDIS_Msk (0x1UL << FSMC_BCR1_WFDIS_Pos)
7090#define FSMC_BCR1_WFDIS FSMC_BCR1_WFDIS_Msk
7091
7092/****************** Bit definition for FSMC_BCR2 register *******************/
7093#define FSMC_BCR2_MBKEN_Pos (0U)
7094#define FSMC_BCR2_MBKEN_Msk (0x1UL << FSMC_BCR2_MBKEN_Pos)
7095#define FSMC_BCR2_MBKEN FSMC_BCR2_MBKEN_Msk
7096#define FSMC_BCR2_MUXEN_Pos (1U)
7097#define FSMC_BCR2_MUXEN_Msk (0x1UL << FSMC_BCR2_MUXEN_Pos)
7098#define FSMC_BCR2_MUXEN FSMC_BCR2_MUXEN_Msk
7099
7100#define FSMC_BCR2_MTYP_Pos (2U)
7101#define FSMC_BCR2_MTYP_Msk (0x3UL << FSMC_BCR2_MTYP_Pos)
7102#define FSMC_BCR2_MTYP FSMC_BCR2_MTYP_Msk
7103#define FSMC_BCR2_MTYP_0 (0x1UL << FSMC_BCR2_MTYP_Pos)
7104#define FSMC_BCR2_MTYP_1 (0x2UL << FSMC_BCR2_MTYP_Pos)
7105
7106#define FSMC_BCR2_MWID_Pos (4U)
7107#define FSMC_BCR2_MWID_Msk (0x3UL << FSMC_BCR2_MWID_Pos)
7108#define FSMC_BCR2_MWID FSMC_BCR2_MWID_Msk
7109#define FSMC_BCR2_MWID_0 (0x1UL << FSMC_BCR2_MWID_Pos)
7110#define FSMC_BCR2_MWID_1 (0x2UL << FSMC_BCR2_MWID_Pos)
7111
7112#define FSMC_BCR2_FACCEN_Pos (6U)
7113#define FSMC_BCR2_FACCEN_Msk (0x1UL << FSMC_BCR2_FACCEN_Pos)
7114#define FSMC_BCR2_FACCEN FSMC_BCR2_FACCEN_Msk
7115#define FSMC_BCR2_BURSTEN_Pos (8U)
7116#define FSMC_BCR2_BURSTEN_Msk (0x1UL << FSMC_BCR2_BURSTEN_Pos)
7117#define FSMC_BCR2_BURSTEN FSMC_BCR2_BURSTEN_Msk
7118#define FSMC_BCR2_WAITPOL_Pos (9U)
7119#define FSMC_BCR2_WAITPOL_Msk (0x1UL << FSMC_BCR2_WAITPOL_Pos)
7120#define FSMC_BCR2_WAITPOL FSMC_BCR2_WAITPOL_Msk
7121#define FSMC_BCR2_WAITCFG_Pos (11U)
7122#define FSMC_BCR2_WAITCFG_Msk (0x1UL << FSMC_BCR2_WAITCFG_Pos)
7123#define FSMC_BCR2_WAITCFG FSMC_BCR2_WAITCFG_Msk
7124#define FSMC_BCR2_WREN_Pos (12U)
7125#define FSMC_BCR2_WREN_Msk (0x1UL << FSMC_BCR2_WREN_Pos)
7126#define FSMC_BCR2_WREN FSMC_BCR2_WREN_Msk
7127#define FSMC_BCR2_WAITEN_Pos (13U)
7128#define FSMC_BCR2_WAITEN_Msk (0x1UL << FSMC_BCR2_WAITEN_Pos)
7129#define FSMC_BCR2_WAITEN FSMC_BCR2_WAITEN_Msk
7130#define FSMC_BCR2_EXTMOD_Pos (14U)
7131#define FSMC_BCR2_EXTMOD_Msk (0x1UL << FSMC_BCR2_EXTMOD_Pos)
7132#define FSMC_BCR2_EXTMOD FSMC_BCR2_EXTMOD_Msk
7133#define FSMC_BCR2_ASYNCWAIT_Pos (15U)
7134#define FSMC_BCR2_ASYNCWAIT_Msk (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)
7135#define FSMC_BCR2_ASYNCWAIT FSMC_BCR2_ASYNCWAIT_Msk
7136#define FSMC_BCR2_CPSIZE_Pos (16U)
7137#define FSMC_BCR2_CPSIZE_Msk (0x7UL << FSMC_BCR2_CPSIZE_Pos)
7138#define FSMC_BCR2_CPSIZE FSMC_BCR2_CPSIZE_Msk
7139#define FSMC_BCR2_CPSIZE_0 (0x1UL << FSMC_BCR2_CPSIZE_Pos)
7140#define FSMC_BCR2_CPSIZE_1 (0x2UL << FSMC_BCR2_CPSIZE_Pos)
7141#define FSMC_BCR2_CPSIZE_2 (0x4UL << FSMC_BCR2_CPSIZE_Pos)
7142#define FSMC_BCR2_CBURSTRW_Pos (19U)
7143#define FSMC_BCR2_CBURSTRW_Msk (0x1UL << FSMC_BCR2_CBURSTRW_Pos)
7144#define FSMC_BCR2_CBURSTRW FSMC_BCR2_CBURSTRW_Msk
7145
7146/****************** Bit definition for FSMC_BCR3 register *******************/
7147#define FSMC_BCR3_MBKEN_Pos (0U)
7148#define FSMC_BCR3_MBKEN_Msk (0x1UL << FSMC_BCR3_MBKEN_Pos)
7149#define FSMC_BCR3_MBKEN FSMC_BCR3_MBKEN_Msk
7150#define FSMC_BCR3_MUXEN_Pos (1U)
7151#define FSMC_BCR3_MUXEN_Msk (0x1UL << FSMC_BCR3_MUXEN_Pos)
7152#define FSMC_BCR3_MUXEN FSMC_BCR3_MUXEN_Msk
7153
7154#define FSMC_BCR3_MTYP_Pos (2U)
7155#define FSMC_BCR3_MTYP_Msk (0x3UL << FSMC_BCR3_MTYP_Pos)
7156#define FSMC_BCR3_MTYP FSMC_BCR3_MTYP_Msk
7157#define FSMC_BCR3_MTYP_0 (0x1UL << FSMC_BCR3_MTYP_Pos)
7158#define FSMC_BCR3_MTYP_1 (0x2UL << FSMC_BCR3_MTYP_Pos)
7159
7160#define FSMC_BCR3_MWID_Pos (4U)
7161#define FSMC_BCR3_MWID_Msk (0x3UL << FSMC_BCR3_MWID_Pos)
7162#define FSMC_BCR3_MWID FSMC_BCR3_MWID_Msk
7163#define FSMC_BCR3_MWID_0 (0x1UL << FSMC_BCR3_MWID_Pos)
7164#define FSMC_BCR3_MWID_1 (0x2UL << FSMC_BCR3_MWID_Pos)
7165
7166#define FSMC_BCR3_FACCEN_Pos (6U)
7167#define FSMC_BCR3_FACCEN_Msk (0x1UL << FSMC_BCR3_FACCEN_Pos)
7168#define FSMC_BCR3_FACCEN FSMC_BCR3_FACCEN_Msk
7169#define FSMC_BCR3_BURSTEN_Pos (8U)
7170#define FSMC_BCR3_BURSTEN_Msk (0x1UL << FSMC_BCR3_BURSTEN_Pos)
7171#define FSMC_BCR3_BURSTEN FSMC_BCR3_BURSTEN_Msk
7172#define FSMC_BCR3_WAITPOL_Pos (9U)
7173#define FSMC_BCR3_WAITPOL_Msk (0x1UL << FSMC_BCR3_WAITPOL_Pos)
7174#define FSMC_BCR3_WAITPOL FSMC_BCR3_WAITPOL_Msk
7175#define FSMC_BCR3_WAITCFG_Pos (11U)
7176#define FSMC_BCR3_WAITCFG_Msk (0x1UL << FSMC_BCR3_WAITCFG_Pos)
7177#define FSMC_BCR3_WAITCFG FSMC_BCR3_WAITCFG_Msk
7178#define FSMC_BCR3_WREN_Pos (12U)
7179#define FSMC_BCR3_WREN_Msk (0x1UL << FSMC_BCR3_WREN_Pos)
7180#define FSMC_BCR3_WREN FSMC_BCR3_WREN_Msk
7181#define FSMC_BCR3_WAITEN_Pos (13U)
7182#define FSMC_BCR3_WAITEN_Msk (0x1UL << FSMC_BCR3_WAITEN_Pos)
7183#define FSMC_BCR3_WAITEN FSMC_BCR3_WAITEN_Msk
7184#define FSMC_BCR3_EXTMOD_Pos (14U)
7185#define FSMC_BCR3_EXTMOD_Msk (0x1UL << FSMC_BCR3_EXTMOD_Pos)
7186#define FSMC_BCR3_EXTMOD FSMC_BCR3_EXTMOD_Msk
7187#define FSMC_BCR3_ASYNCWAIT_Pos (15U)
7188#define FSMC_BCR3_ASYNCWAIT_Msk (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)
7189#define FSMC_BCR3_ASYNCWAIT FSMC_BCR3_ASYNCWAIT_Msk
7190#define FSMC_BCR3_CPSIZE_Pos (16U)
7191#define FSMC_BCR3_CPSIZE_Msk (0x7UL << FSMC_BCR3_CPSIZE_Pos)
7192#define FSMC_BCR3_CPSIZE FSMC_BCR3_CPSIZE_Msk
7193#define FSMC_BCR3_CPSIZE_0 (0x1UL << FSMC_BCR3_CPSIZE_Pos)
7194#define FSMC_BCR3_CPSIZE_1 (0x2UL << FSMC_BCR3_CPSIZE_Pos)
7195#define FSMC_BCR3_CPSIZE_2 (0x4UL << FSMC_BCR3_CPSIZE_Pos)
7196#define FSMC_BCR3_CBURSTRW_Pos (19U)
7197#define FSMC_BCR3_CBURSTRW_Msk (0x1UL << FSMC_BCR3_CBURSTRW_Pos)
7198#define FSMC_BCR3_CBURSTRW FSMC_BCR3_CBURSTRW_Msk
7199
7200/****************** Bit definition for FSMC_BCR4 register *******************/
7201#define FSMC_BCR4_MBKEN_Pos (0U)
7202#define FSMC_BCR4_MBKEN_Msk (0x1UL << FSMC_BCR4_MBKEN_Pos)
7203#define FSMC_BCR4_MBKEN FSMC_BCR4_MBKEN_Msk
7204#define FSMC_BCR4_MUXEN_Pos (1U)
7205#define FSMC_BCR4_MUXEN_Msk (0x1UL << FSMC_BCR4_MUXEN_Pos)
7206#define FSMC_BCR4_MUXEN FSMC_BCR4_MUXEN_Msk
7207
7208#define FSMC_BCR4_MTYP_Pos (2U)
7209#define FSMC_BCR4_MTYP_Msk (0x3UL << FSMC_BCR4_MTYP_Pos)
7210#define FSMC_BCR4_MTYP FSMC_BCR4_MTYP_Msk
7211#define FSMC_BCR4_MTYP_0 (0x1UL << FSMC_BCR4_MTYP_Pos)
7212#define FSMC_BCR4_MTYP_1 (0x2UL << FSMC_BCR4_MTYP_Pos)
7213
7214#define FSMC_BCR4_MWID_Pos (4U)
7215#define FSMC_BCR4_MWID_Msk (0x3UL << FSMC_BCR4_MWID_Pos)
7216#define FSMC_BCR4_MWID FSMC_BCR4_MWID_Msk
7217#define FSMC_BCR4_MWID_0 (0x1UL << FSMC_BCR4_MWID_Pos)
7218#define FSMC_BCR4_MWID_1 (0x2UL << FSMC_BCR4_MWID_Pos)
7219
7220#define FSMC_BCR4_FACCEN_Pos (6U)
7221#define FSMC_BCR4_FACCEN_Msk (0x1UL << FSMC_BCR4_FACCEN_Pos)
7222#define FSMC_BCR4_FACCEN FSMC_BCR4_FACCEN_Msk
7223#define FSMC_BCR4_BURSTEN_Pos (8U)
7224#define FSMC_BCR4_BURSTEN_Msk (0x1UL << FSMC_BCR4_BURSTEN_Pos)
7225#define FSMC_BCR4_BURSTEN FSMC_BCR4_BURSTEN_Msk
7226#define FSMC_BCR4_WAITPOL_Pos (9U)
7227#define FSMC_BCR4_WAITPOL_Msk (0x1UL << FSMC_BCR4_WAITPOL_Pos)
7228#define FSMC_BCR4_WAITPOL FSMC_BCR4_WAITPOL_Msk
7229#define FSMC_BCR4_WAITCFG_Pos (11U)
7230#define FSMC_BCR4_WAITCFG_Msk (0x1UL << FSMC_BCR4_WAITCFG_Pos)
7231#define FSMC_BCR4_WAITCFG FSMC_BCR4_WAITCFG_Msk
7232#define FSMC_BCR4_WREN_Pos (12U)
7233#define FSMC_BCR4_WREN_Msk (0x1UL << FSMC_BCR4_WREN_Pos)
7234#define FSMC_BCR4_WREN FSMC_BCR4_WREN_Msk
7235#define FSMC_BCR4_WAITEN_Pos (13U)
7236#define FSMC_BCR4_WAITEN_Msk (0x1UL << FSMC_BCR4_WAITEN_Pos)
7237#define FSMC_BCR4_WAITEN FSMC_BCR4_WAITEN_Msk
7238#define FSMC_BCR4_EXTMOD_Pos (14U)
7239#define FSMC_BCR4_EXTMOD_Msk (0x1UL << FSMC_BCR4_EXTMOD_Pos)
7240#define FSMC_BCR4_EXTMOD FSMC_BCR4_EXTMOD_Msk
7241#define FSMC_BCR4_ASYNCWAIT_Pos (15U)
7242#define FSMC_BCR4_ASYNCWAIT_Msk (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)
7243#define FSMC_BCR4_ASYNCWAIT FSMC_BCR4_ASYNCWAIT_Msk
7244#define FSMC_BCR4_CPSIZE_Pos (16U)
7245#define FSMC_BCR4_CPSIZE_Msk (0x7UL << FSMC_BCR4_CPSIZE_Pos)
7246#define FSMC_BCR4_CPSIZE FSMC_BCR4_CPSIZE_Msk
7247#define FSMC_BCR4_CPSIZE_0 (0x1UL << FSMC_BCR4_CPSIZE_Pos)
7248#define FSMC_BCR4_CPSIZE_1 (0x2UL << FSMC_BCR4_CPSIZE_Pos)
7249#define FSMC_BCR4_CPSIZE_2 (0x4UL << FSMC_BCR4_CPSIZE_Pos)
7250#define FSMC_BCR4_CBURSTRW_Pos (19U)
7251#define FSMC_BCR4_CBURSTRW_Msk (0x1UL << FSMC_BCR4_CBURSTRW_Pos)
7252#define FSMC_BCR4_CBURSTRW FSMC_BCR4_CBURSTRW_Msk
7253
7254/****************** Bit definition for FSMC_BTR1 register ******************/
7255#define FSMC_BTR1_ADDSET_Pos (0U)
7256#define FSMC_BTR1_ADDSET_Msk (0xFUL << FSMC_BTR1_ADDSET_Pos)
7257#define FSMC_BTR1_ADDSET FSMC_BTR1_ADDSET_Msk
7258#define FSMC_BTR1_ADDSET_0 (0x1UL << FSMC_BTR1_ADDSET_Pos)
7259#define FSMC_BTR1_ADDSET_1 (0x2UL << FSMC_BTR1_ADDSET_Pos)
7260#define FSMC_BTR1_ADDSET_2 (0x4UL << FSMC_BTR1_ADDSET_Pos)
7261#define FSMC_BTR1_ADDSET_3 (0x8UL << FSMC_BTR1_ADDSET_Pos)
7262
7263#define FSMC_BTR1_ADDHLD_Pos (4U)
7264#define FSMC_BTR1_ADDHLD_Msk (0xFUL << FSMC_BTR1_ADDHLD_Pos)
7265#define FSMC_BTR1_ADDHLD FSMC_BTR1_ADDHLD_Msk
7266#define FSMC_BTR1_ADDHLD_0 (0x1UL << FSMC_BTR1_ADDHLD_Pos)
7267#define FSMC_BTR1_ADDHLD_1 (0x2UL << FSMC_BTR1_ADDHLD_Pos)
7268#define FSMC_BTR1_ADDHLD_2 (0x4UL << FSMC_BTR1_ADDHLD_Pos)
7269#define FSMC_BTR1_ADDHLD_3 (0x8UL << FSMC_BTR1_ADDHLD_Pos)
7270
7271#define FSMC_BTR1_DATAST_Pos (8U)
7272#define FSMC_BTR1_DATAST_Msk (0xFFUL << FSMC_BTR1_DATAST_Pos)
7273#define FSMC_BTR1_DATAST FSMC_BTR1_DATAST_Msk
7274#define FSMC_BTR1_DATAST_0 (0x01UL << FSMC_BTR1_DATAST_Pos)
7275#define FSMC_BTR1_DATAST_1 (0x02UL << FSMC_BTR1_DATAST_Pos)
7276#define FSMC_BTR1_DATAST_2 (0x04UL << FSMC_BTR1_DATAST_Pos)
7277#define FSMC_BTR1_DATAST_3 (0x08UL << FSMC_BTR1_DATAST_Pos)
7278#define FSMC_BTR1_DATAST_4 (0x10UL << FSMC_BTR1_DATAST_Pos)
7279#define FSMC_BTR1_DATAST_5 (0x20UL << FSMC_BTR1_DATAST_Pos)
7280#define FSMC_BTR1_DATAST_6 (0x40UL << FSMC_BTR1_DATAST_Pos)
7281#define FSMC_BTR1_DATAST_7 (0x80UL << FSMC_BTR1_DATAST_Pos)
7282
7283#define FSMC_BTR1_BUSTURN_Pos (16U)
7284#define FSMC_BTR1_BUSTURN_Msk (0xFUL << FSMC_BTR1_BUSTURN_Pos)
7285#define FSMC_BTR1_BUSTURN FSMC_BTR1_BUSTURN_Msk
7286#define FSMC_BTR1_BUSTURN_0 (0x1UL << FSMC_BTR1_BUSTURN_Pos)
7287#define FSMC_BTR1_BUSTURN_1 (0x2UL << FSMC_BTR1_BUSTURN_Pos)
7288#define FSMC_BTR1_BUSTURN_2 (0x4UL << FSMC_BTR1_BUSTURN_Pos)
7289#define FSMC_BTR1_BUSTURN_3 (0x8UL << FSMC_BTR1_BUSTURN_Pos)
7290
7291#define FSMC_BTR1_CLKDIV_Pos (20U)
7292#define FSMC_BTR1_CLKDIV_Msk (0xFUL << FSMC_BTR1_CLKDIV_Pos)
7293#define FSMC_BTR1_CLKDIV FSMC_BTR1_CLKDIV_Msk
7294#define FSMC_BTR1_CLKDIV_0 (0x1UL << FSMC_BTR1_CLKDIV_Pos)
7295#define FSMC_BTR1_CLKDIV_1 (0x2UL << FSMC_BTR1_CLKDIV_Pos)
7296#define FSMC_BTR1_CLKDIV_2 (0x4UL << FSMC_BTR1_CLKDIV_Pos)
7297#define FSMC_BTR1_CLKDIV_3 (0x8UL << FSMC_BTR1_CLKDIV_Pos)
7298
7299#define FSMC_BTR1_DATLAT_Pos (24U)
7300#define FSMC_BTR1_DATLAT_Msk (0xFUL << FSMC_BTR1_DATLAT_Pos)
7301#define FSMC_BTR1_DATLAT FSMC_BTR1_DATLAT_Msk
7302#define FSMC_BTR1_DATLAT_0 (0x1UL << FSMC_BTR1_DATLAT_Pos)
7303#define FSMC_BTR1_DATLAT_1 (0x2UL << FSMC_BTR1_DATLAT_Pos)
7304#define FSMC_BTR1_DATLAT_2 (0x4UL << FSMC_BTR1_DATLAT_Pos)
7305#define FSMC_BTR1_DATLAT_3 (0x8UL << FSMC_BTR1_DATLAT_Pos)
7306
7307#define FSMC_BTR1_ACCMOD_Pos (28U)
7308#define FSMC_BTR1_ACCMOD_Msk (0x3UL << FSMC_BTR1_ACCMOD_Pos)
7309#define FSMC_BTR1_ACCMOD FSMC_BTR1_ACCMOD_Msk
7310#define FSMC_BTR1_ACCMOD_0 (0x1UL << FSMC_BTR1_ACCMOD_Pos)
7311#define FSMC_BTR1_ACCMOD_1 (0x2UL << FSMC_BTR1_ACCMOD_Pos)
7312
7313/****************** Bit definition for FSMC_BTR2 register *******************/
7314#define FSMC_BTR2_ADDSET_Pos (0U)
7315#define FSMC_BTR2_ADDSET_Msk (0xFUL << FSMC_BTR2_ADDSET_Pos)
7316#define FSMC_BTR2_ADDSET FSMC_BTR2_ADDSET_Msk
7317#define FSMC_BTR2_ADDSET_0 (0x1UL << FSMC_BTR2_ADDSET_Pos)
7318#define FSMC_BTR2_ADDSET_1 (0x2UL << FSMC_BTR2_ADDSET_Pos)
7319#define FSMC_BTR2_ADDSET_2 (0x4UL << FSMC_BTR2_ADDSET_Pos)
7320#define FSMC_BTR2_ADDSET_3 (0x8UL << FSMC_BTR2_ADDSET_Pos)
7321
7322#define FSMC_BTR2_ADDHLD_Pos (4U)
7323#define FSMC_BTR2_ADDHLD_Msk (0xFUL << FSMC_BTR2_ADDHLD_Pos)
7324#define FSMC_BTR2_ADDHLD FSMC_BTR2_ADDHLD_Msk
7325#define FSMC_BTR2_ADDHLD_0 (0x1UL << FSMC_BTR2_ADDHLD_Pos)
7326#define FSMC_BTR2_ADDHLD_1 (0x2UL << FSMC_BTR2_ADDHLD_Pos)
7327#define FSMC_BTR2_ADDHLD_2 (0x4UL << FSMC_BTR2_ADDHLD_Pos)
7328#define FSMC_BTR2_ADDHLD_3 (0x8UL << FSMC_BTR2_ADDHLD_Pos)
7329
7330#define FSMC_BTR2_DATAST_Pos (8U)
7331#define FSMC_BTR2_DATAST_Msk (0xFFUL << FSMC_BTR2_DATAST_Pos)
7332#define FSMC_BTR2_DATAST FSMC_BTR2_DATAST_Msk
7333#define FSMC_BTR2_DATAST_0 (0x01UL << FSMC_BTR2_DATAST_Pos)
7334#define FSMC_BTR2_DATAST_1 (0x02UL << FSMC_BTR2_DATAST_Pos)
7335#define FSMC_BTR2_DATAST_2 (0x04UL << FSMC_BTR2_DATAST_Pos)
7336#define FSMC_BTR2_DATAST_3 (0x08UL << FSMC_BTR2_DATAST_Pos)
7337#define FSMC_BTR2_DATAST_4 (0x10UL << FSMC_BTR2_DATAST_Pos)
7338#define FSMC_BTR2_DATAST_5 (0x20UL << FSMC_BTR2_DATAST_Pos)
7339#define FSMC_BTR2_DATAST_6 (0x40UL << FSMC_BTR2_DATAST_Pos)
7340#define FSMC_BTR2_DATAST_7 (0x80UL << FSMC_BTR2_DATAST_Pos)
7341
7342#define FSMC_BTR2_BUSTURN_Pos (16U)
7343#define FSMC_BTR2_BUSTURN_Msk (0xFUL << FSMC_BTR2_BUSTURN_Pos)
7344#define FSMC_BTR2_BUSTURN FSMC_BTR2_BUSTURN_Msk
7345#define FSMC_BTR2_BUSTURN_0 (0x1UL << FSMC_BTR2_BUSTURN_Pos)
7346#define FSMC_BTR2_BUSTURN_1 (0x2UL << FSMC_BTR2_BUSTURN_Pos)
7347#define FSMC_BTR2_BUSTURN_2 (0x4UL << FSMC_BTR2_BUSTURN_Pos)
7348#define FSMC_BTR2_BUSTURN_3 (0x8UL << FSMC_BTR2_BUSTURN_Pos)
7349
7350#define FSMC_BTR2_CLKDIV_Pos (20U)
7351#define FSMC_BTR2_CLKDIV_Msk (0xFUL << FSMC_BTR2_CLKDIV_Pos)
7352#define FSMC_BTR2_CLKDIV FSMC_BTR2_CLKDIV_Msk
7353#define FSMC_BTR2_CLKDIV_0 (0x1UL << FSMC_BTR2_CLKDIV_Pos)
7354#define FSMC_BTR2_CLKDIV_1 (0x2UL << FSMC_BTR2_CLKDIV_Pos)
7355#define FSMC_BTR2_CLKDIV_2 (0x4UL << FSMC_BTR2_CLKDIV_Pos)
7356#define FSMC_BTR2_CLKDIV_3 (0x8UL << FSMC_BTR2_CLKDIV_Pos)
7357
7358#define FSMC_BTR2_DATLAT_Pos (24U)
7359#define FSMC_BTR2_DATLAT_Msk (0xFUL << FSMC_BTR2_DATLAT_Pos)
7360#define FSMC_BTR2_DATLAT FSMC_BTR2_DATLAT_Msk
7361#define FSMC_BTR2_DATLAT_0 (0x1UL << FSMC_BTR2_DATLAT_Pos)
7362#define FSMC_BTR2_DATLAT_1 (0x2UL << FSMC_BTR2_DATLAT_Pos)
7363#define FSMC_BTR2_DATLAT_2 (0x4UL << FSMC_BTR2_DATLAT_Pos)
7364#define FSMC_BTR2_DATLAT_3 (0x8UL << FSMC_BTR2_DATLAT_Pos)
7365
7366#define FSMC_BTR2_ACCMOD_Pos (28U)
7367#define FSMC_BTR2_ACCMOD_Msk (0x3UL << FSMC_BTR2_ACCMOD_Pos)
7368#define FSMC_BTR2_ACCMOD FSMC_BTR2_ACCMOD_Msk
7369#define FSMC_BTR2_ACCMOD_0 (0x1UL << FSMC_BTR2_ACCMOD_Pos)
7370#define FSMC_BTR2_ACCMOD_1 (0x2UL << FSMC_BTR2_ACCMOD_Pos)
7371
7372/******************* Bit definition for FSMC_BTR3 register *******************/
7373#define FSMC_BTR3_ADDSET_Pos (0U)
7374#define FSMC_BTR3_ADDSET_Msk (0xFUL << FSMC_BTR3_ADDSET_Pos)
7375#define FSMC_BTR3_ADDSET FSMC_BTR3_ADDSET_Msk
7376#define FSMC_BTR3_ADDSET_0 (0x1UL << FSMC_BTR3_ADDSET_Pos)
7377#define FSMC_BTR3_ADDSET_1 (0x2UL << FSMC_BTR3_ADDSET_Pos)
7378#define FSMC_BTR3_ADDSET_2 (0x4UL << FSMC_BTR3_ADDSET_Pos)
7379#define FSMC_BTR3_ADDSET_3 (0x8UL << FSMC_BTR3_ADDSET_Pos)
7380
7381#define FSMC_BTR3_ADDHLD_Pos (4U)
7382#define FSMC_BTR3_ADDHLD_Msk (0xFUL << FSMC_BTR3_ADDHLD_Pos)
7383#define FSMC_BTR3_ADDHLD FSMC_BTR3_ADDHLD_Msk
7384#define FSMC_BTR3_ADDHLD_0 (0x1UL << FSMC_BTR3_ADDHLD_Pos)
7385#define FSMC_BTR3_ADDHLD_1 (0x2UL << FSMC_BTR3_ADDHLD_Pos)
7386#define FSMC_BTR3_ADDHLD_2 (0x4UL << FSMC_BTR3_ADDHLD_Pos)
7387#define FSMC_BTR3_ADDHLD_3 (0x8UL << FSMC_BTR3_ADDHLD_Pos)
7388
7389#define FSMC_BTR3_DATAST_Pos (8U)
7390#define FSMC_BTR3_DATAST_Msk (0xFFUL << FSMC_BTR3_DATAST_Pos)
7391#define FSMC_BTR3_DATAST FSMC_BTR3_DATAST_Msk
7392#define FSMC_BTR3_DATAST_0 (0x01UL << FSMC_BTR3_DATAST_Pos)
7393#define FSMC_BTR3_DATAST_1 (0x02UL << FSMC_BTR3_DATAST_Pos)
7394#define FSMC_BTR3_DATAST_2 (0x04UL << FSMC_BTR3_DATAST_Pos)
7395#define FSMC_BTR3_DATAST_3 (0x08UL << FSMC_BTR3_DATAST_Pos)
7396#define FSMC_BTR3_DATAST_4 (0x10UL << FSMC_BTR3_DATAST_Pos)
7397#define FSMC_BTR3_DATAST_5 (0x20UL << FSMC_BTR3_DATAST_Pos)
7398#define FSMC_BTR3_DATAST_6 (0x40UL << FSMC_BTR3_DATAST_Pos)
7399#define FSMC_BTR3_DATAST_7 (0x80UL << FSMC_BTR3_DATAST_Pos)
7400
7401#define FSMC_BTR3_BUSTURN_Pos (16U)
7402#define FSMC_BTR3_BUSTURN_Msk (0xFUL << FSMC_BTR3_BUSTURN_Pos)
7403#define FSMC_BTR3_BUSTURN FSMC_BTR3_BUSTURN_Msk
7404#define FSMC_BTR3_BUSTURN_0 (0x1UL << FSMC_BTR3_BUSTURN_Pos)
7405#define FSMC_BTR3_BUSTURN_1 (0x2UL << FSMC_BTR3_BUSTURN_Pos)
7406#define FSMC_BTR3_BUSTURN_2 (0x4UL << FSMC_BTR3_BUSTURN_Pos)
7407#define FSMC_BTR3_BUSTURN_3 (0x8UL << FSMC_BTR3_BUSTURN_Pos)
7408
7409#define FSMC_BTR3_CLKDIV_Pos (20U)
7410#define FSMC_BTR3_CLKDIV_Msk (0xFUL << FSMC_BTR3_CLKDIV_Pos)
7411#define FSMC_BTR3_CLKDIV FSMC_BTR3_CLKDIV_Msk
7412#define FSMC_BTR3_CLKDIV_0 (0x1UL << FSMC_BTR3_CLKDIV_Pos)
7413#define FSMC_BTR3_CLKDIV_1 (0x2UL << FSMC_BTR3_CLKDIV_Pos)
7414#define FSMC_BTR3_CLKDIV_2 (0x4UL << FSMC_BTR3_CLKDIV_Pos)
7415#define FSMC_BTR3_CLKDIV_3 (0x8UL << FSMC_BTR3_CLKDIV_Pos)
7416
7417#define FSMC_BTR3_DATLAT_Pos (24U)
7418#define FSMC_BTR3_DATLAT_Msk (0xFUL << FSMC_BTR3_DATLAT_Pos)
7419#define FSMC_BTR3_DATLAT FSMC_BTR3_DATLAT_Msk
7420#define FSMC_BTR3_DATLAT_0 (0x1UL << FSMC_BTR3_DATLAT_Pos)
7421#define FSMC_BTR3_DATLAT_1 (0x2UL << FSMC_BTR3_DATLAT_Pos)
7422#define FSMC_BTR3_DATLAT_2 (0x4UL << FSMC_BTR3_DATLAT_Pos)
7423#define FSMC_BTR3_DATLAT_3 (0x8UL << FSMC_BTR3_DATLAT_Pos)
7424
7425#define FSMC_BTR3_ACCMOD_Pos (28U)
7426#define FSMC_BTR3_ACCMOD_Msk (0x3UL << FSMC_BTR3_ACCMOD_Pos)
7427#define FSMC_BTR3_ACCMOD FSMC_BTR3_ACCMOD_Msk
7428#define FSMC_BTR3_ACCMOD_0 (0x1UL << FSMC_BTR3_ACCMOD_Pos)
7429#define FSMC_BTR3_ACCMOD_1 (0x2UL << FSMC_BTR3_ACCMOD_Pos)
7430
7431/****************** Bit definition for FSMC_BTR4 register *******************/
7432#define FSMC_BTR4_ADDSET_Pos (0U)
7433#define FSMC_BTR4_ADDSET_Msk (0xFUL << FSMC_BTR4_ADDSET_Pos)
7434#define FSMC_BTR4_ADDSET FSMC_BTR4_ADDSET_Msk
7435#define FSMC_BTR4_ADDSET_0 (0x1UL << FSMC_BTR4_ADDSET_Pos)
7436#define FSMC_BTR4_ADDSET_1 (0x2UL << FSMC_BTR4_ADDSET_Pos)
7437#define FSMC_BTR4_ADDSET_2 (0x4UL << FSMC_BTR4_ADDSET_Pos)
7438#define FSMC_BTR4_ADDSET_3 (0x8UL << FSMC_BTR4_ADDSET_Pos)
7439
7440#define FSMC_BTR4_ADDHLD_Pos (4U)
7441#define FSMC_BTR4_ADDHLD_Msk (0xFUL << FSMC_BTR4_ADDHLD_Pos)
7442#define FSMC_BTR4_ADDHLD FSMC_BTR4_ADDHLD_Msk
7443#define FSMC_BTR4_ADDHLD_0 (0x1UL << FSMC_BTR4_ADDHLD_Pos)
7444#define FSMC_BTR4_ADDHLD_1 (0x2UL << FSMC_BTR4_ADDHLD_Pos)
7445#define FSMC_BTR4_ADDHLD_2 (0x4UL << FSMC_BTR4_ADDHLD_Pos)
7446#define FSMC_BTR4_ADDHLD_3 (0x8UL << FSMC_BTR4_ADDHLD_Pos)
7447
7448#define FSMC_BTR4_DATAST_Pos (8U)
7449#define FSMC_BTR4_DATAST_Msk (0xFFUL << FSMC_BTR4_DATAST_Pos)
7450#define FSMC_BTR4_DATAST FSMC_BTR4_DATAST_Msk
7451#define FSMC_BTR4_DATAST_0 (0x01UL << FSMC_BTR4_DATAST_Pos)
7452#define FSMC_BTR4_DATAST_1 (0x02UL << FSMC_BTR4_DATAST_Pos)
7453#define FSMC_BTR4_DATAST_2 (0x04UL << FSMC_BTR4_DATAST_Pos)
7454#define FSMC_BTR4_DATAST_3 (0x08UL << FSMC_BTR4_DATAST_Pos)
7455#define FSMC_BTR4_DATAST_4 (0x10UL << FSMC_BTR4_DATAST_Pos)
7456#define FSMC_BTR4_DATAST_5 (0x20UL << FSMC_BTR4_DATAST_Pos)
7457#define FSMC_BTR4_DATAST_6 (0x40UL << FSMC_BTR4_DATAST_Pos)
7458#define FSMC_BTR4_DATAST_7 (0x80UL << FSMC_BTR4_DATAST_Pos)
7459
7460#define FSMC_BTR4_BUSTURN_Pos (16U)
7461#define FSMC_BTR4_BUSTURN_Msk (0xFUL << FSMC_BTR4_BUSTURN_Pos)
7462#define FSMC_BTR4_BUSTURN FSMC_BTR4_BUSTURN_Msk
7463#define FSMC_BTR4_BUSTURN_0 (0x1UL << FSMC_BTR4_BUSTURN_Pos)
7464#define FSMC_BTR4_BUSTURN_1 (0x2UL << FSMC_BTR4_BUSTURN_Pos)
7465#define FSMC_BTR4_BUSTURN_2 (0x4UL << FSMC_BTR4_BUSTURN_Pos)
7466#define FSMC_BTR4_BUSTURN_3 (0x8UL << FSMC_BTR4_BUSTURN_Pos)
7467
7468#define FSMC_BTR4_CLKDIV_Pos (20U)
7469#define FSMC_BTR4_CLKDIV_Msk (0xFUL << FSMC_BTR4_CLKDIV_Pos)
7470#define FSMC_BTR4_CLKDIV FSMC_BTR4_CLKDIV_Msk
7471#define FSMC_BTR4_CLKDIV_0 (0x1UL << FSMC_BTR4_CLKDIV_Pos)
7472#define FSMC_BTR4_CLKDIV_1 (0x2UL << FSMC_BTR4_CLKDIV_Pos)
7473#define FSMC_BTR4_CLKDIV_2 (0x4UL << FSMC_BTR4_CLKDIV_Pos)
7474#define FSMC_BTR4_CLKDIV_3 (0x8UL << FSMC_BTR4_CLKDIV_Pos)
7475
7476#define FSMC_BTR4_DATLAT_Pos (24U)
7477#define FSMC_BTR4_DATLAT_Msk (0xFUL << FSMC_BTR4_DATLAT_Pos)
7478#define FSMC_BTR4_DATLAT FSMC_BTR4_DATLAT_Msk
7479#define FSMC_BTR4_DATLAT_0 (0x1UL << FSMC_BTR4_DATLAT_Pos)
7480#define FSMC_BTR4_DATLAT_1 (0x2UL << FSMC_BTR4_DATLAT_Pos)
7481#define FSMC_BTR4_DATLAT_2 (0x4UL << FSMC_BTR4_DATLAT_Pos)
7482#define FSMC_BTR4_DATLAT_3 (0x8UL << FSMC_BTR4_DATLAT_Pos)
7483
7484#define FSMC_BTR4_ACCMOD_Pos (28U)
7485#define FSMC_BTR4_ACCMOD_Msk (0x3UL << FSMC_BTR4_ACCMOD_Pos)
7486#define FSMC_BTR4_ACCMOD FSMC_BTR4_ACCMOD_Msk
7487#define FSMC_BTR4_ACCMOD_0 (0x1UL << FSMC_BTR4_ACCMOD_Pos)
7488#define FSMC_BTR4_ACCMOD_1 (0x2UL << FSMC_BTR4_ACCMOD_Pos)
7489
7490/****************** Bit definition for FSMC_BWTR1 register ******************/
7491#define FSMC_BWTR1_ADDSET_Pos (0U)
7492#define FSMC_BWTR1_ADDSET_Msk (0xFUL << FSMC_BWTR1_ADDSET_Pos)
7493#define FSMC_BWTR1_ADDSET FSMC_BWTR1_ADDSET_Msk
7494#define FSMC_BWTR1_ADDSET_0 (0x1UL << FSMC_BWTR1_ADDSET_Pos)
7495#define FSMC_BWTR1_ADDSET_1 (0x2UL << FSMC_BWTR1_ADDSET_Pos)
7496#define FSMC_BWTR1_ADDSET_2 (0x4UL << FSMC_BWTR1_ADDSET_Pos)
7497#define FSMC_BWTR1_ADDSET_3 (0x8UL << FSMC_BWTR1_ADDSET_Pos)
7498
7499#define FSMC_BWTR1_ADDHLD_Pos (4U)
7500#define FSMC_BWTR1_ADDHLD_Msk (0xFUL << FSMC_BWTR1_ADDHLD_Pos)
7501#define FSMC_BWTR1_ADDHLD FSMC_BWTR1_ADDHLD_Msk
7502#define FSMC_BWTR1_ADDHLD_0 (0x1UL << FSMC_BWTR1_ADDHLD_Pos)
7503#define FSMC_BWTR1_ADDHLD_1 (0x2UL << FSMC_BWTR1_ADDHLD_Pos)
7504#define FSMC_BWTR1_ADDHLD_2 (0x4UL << FSMC_BWTR1_ADDHLD_Pos)
7505#define FSMC_BWTR1_ADDHLD_3 (0x8UL << FSMC_BWTR1_ADDHLD_Pos)
7506
7507#define FSMC_BWTR1_DATAST_Pos (8U)
7508#define FSMC_BWTR1_DATAST_Msk (0xFFUL << FSMC_BWTR1_DATAST_Pos)
7509#define FSMC_BWTR1_DATAST FSMC_BWTR1_DATAST_Msk
7510#define FSMC_BWTR1_DATAST_0 (0x01UL << FSMC_BWTR1_DATAST_Pos)
7511#define FSMC_BWTR1_DATAST_1 (0x02UL << FSMC_BWTR1_DATAST_Pos)
7512#define FSMC_BWTR1_DATAST_2 (0x04UL << FSMC_BWTR1_DATAST_Pos)
7513#define FSMC_BWTR1_DATAST_3 (0x08UL << FSMC_BWTR1_DATAST_Pos)
7514#define FSMC_BWTR1_DATAST_4 (0x10UL << FSMC_BWTR1_DATAST_Pos)
7515#define FSMC_BWTR1_DATAST_5 (0x20UL << FSMC_BWTR1_DATAST_Pos)
7516#define FSMC_BWTR1_DATAST_6 (0x40UL << FSMC_BWTR1_DATAST_Pos)
7517#define FSMC_BWTR1_DATAST_7 (0x80UL << FSMC_BWTR1_DATAST_Pos)
7518
7519#define FSMC_BWTR1_BUSTURN_Pos (16U)
7520#define FSMC_BWTR1_BUSTURN_Msk (0xFUL << FSMC_BWTR1_BUSTURN_Pos)
7521#define FSMC_BWTR1_BUSTURN FSMC_BWTR1_BUSTURN_Msk
7522#define FSMC_BWTR1_BUSTURN_0 (0x1UL << FSMC_BWTR1_BUSTURN_Pos)
7523#define FSMC_BWTR1_BUSTURN_1 (0x2UL << FSMC_BWTR1_BUSTURN_Pos)
7524#define FSMC_BWTR1_BUSTURN_2 (0x4UL << FSMC_BWTR1_BUSTURN_Pos)
7525#define FSMC_BWTR1_BUSTURN_3 (0x8UL << FSMC_BWTR1_BUSTURN_Pos)
7526
7527#define FSMC_BWTR1_ACCMOD_Pos (28U)
7528#define FSMC_BWTR1_ACCMOD_Msk (0x3UL << FSMC_BWTR1_ACCMOD_Pos)
7529#define FSMC_BWTR1_ACCMOD FSMC_BWTR1_ACCMOD_Msk
7530#define FSMC_BWTR1_ACCMOD_0 (0x1UL << FSMC_BWTR1_ACCMOD_Pos)
7531#define FSMC_BWTR1_ACCMOD_1 (0x2UL << FSMC_BWTR1_ACCMOD_Pos)
7532
7533/****************** Bit definition for FSMC_BWTR2 register ******************/
7534#define FSMC_BWTR2_ADDSET_Pos (0U)
7535#define FSMC_BWTR2_ADDSET_Msk (0xFUL << FSMC_BWTR2_ADDSET_Pos)
7536#define FSMC_BWTR2_ADDSET FSMC_BWTR2_ADDSET_Msk
7537#define FSMC_BWTR2_ADDSET_0 (0x1UL << FSMC_BWTR2_ADDSET_Pos)
7538#define FSMC_BWTR2_ADDSET_1 (0x2UL << FSMC_BWTR2_ADDSET_Pos)
7539#define FSMC_BWTR2_ADDSET_2 (0x4UL << FSMC_BWTR2_ADDSET_Pos)
7540#define FSMC_BWTR2_ADDSET_3 (0x8UL << FSMC_BWTR2_ADDSET_Pos)
7541
7542#define FSMC_BWTR2_ADDHLD_Pos (4U)
7543#define FSMC_BWTR2_ADDHLD_Msk (0xFUL << FSMC_BWTR2_ADDHLD_Pos)
7544#define FSMC_BWTR2_ADDHLD FSMC_BWTR2_ADDHLD_Msk
7545#define FSMC_BWTR2_ADDHLD_0 (0x1UL << FSMC_BWTR2_ADDHLD_Pos)
7546#define FSMC_BWTR2_ADDHLD_1 (0x2UL << FSMC_BWTR2_ADDHLD_Pos)
7547#define FSMC_BWTR2_ADDHLD_2 (0x4UL << FSMC_BWTR2_ADDHLD_Pos)
7548#define FSMC_BWTR2_ADDHLD_3 (0x8UL << FSMC_BWTR2_ADDHLD_Pos)
7549
7550#define FSMC_BWTR2_DATAST_Pos (8U)
7551#define FSMC_BWTR2_DATAST_Msk (0xFFUL << FSMC_BWTR2_DATAST_Pos)
7552#define FSMC_BWTR2_DATAST FSMC_BWTR2_DATAST_Msk
7553#define FSMC_BWTR2_DATAST_0 (0x01UL << FSMC_BWTR2_DATAST_Pos)
7554#define FSMC_BWTR2_DATAST_1 (0x02UL << FSMC_BWTR2_DATAST_Pos)
7555#define FSMC_BWTR2_DATAST_2 (0x04UL << FSMC_BWTR2_DATAST_Pos)
7556#define FSMC_BWTR2_DATAST_3 (0x08UL << FSMC_BWTR2_DATAST_Pos)
7557#define FSMC_BWTR2_DATAST_4 (0x10UL << FSMC_BWTR2_DATAST_Pos)
7558#define FSMC_BWTR2_DATAST_5 (0x20UL << FSMC_BWTR2_DATAST_Pos)
7559#define FSMC_BWTR2_DATAST_6 (0x40UL << FSMC_BWTR2_DATAST_Pos)
7560#define FSMC_BWTR2_DATAST_7 (0x80UL << FSMC_BWTR2_DATAST_Pos)
7561
7562#define FSMC_BWTR2_BUSTURN_Pos (16U)
7563#define FSMC_BWTR2_BUSTURN_Msk (0xFUL << FSMC_BWTR2_BUSTURN_Pos)
7564#define FSMC_BWTR2_BUSTURN FSMC_BWTR2_BUSTURN_Msk
7565#define FSMC_BWTR2_BUSTURN_0 (0x1UL << FSMC_BWTR2_BUSTURN_Pos)
7566#define FSMC_BWTR2_BUSTURN_1 (0x2UL << FSMC_BWTR2_BUSTURN_Pos)
7567#define FSMC_BWTR2_BUSTURN_2 (0x4UL << FSMC_BWTR2_BUSTURN_Pos)
7568#define FSMC_BWTR2_BUSTURN_3 (0x8UL << FSMC_BWTR2_BUSTURN_Pos)
7569
7570#define FSMC_BWTR2_ACCMOD_Pos (28U)
7571#define FSMC_BWTR2_ACCMOD_Msk (0x3UL << FSMC_BWTR2_ACCMOD_Pos)
7572#define FSMC_BWTR2_ACCMOD FSMC_BWTR2_ACCMOD_Msk
7573#define FSMC_BWTR2_ACCMOD_0 (0x1UL << FSMC_BWTR2_ACCMOD_Pos)
7574#define FSMC_BWTR2_ACCMOD_1 (0x2UL << FSMC_BWTR2_ACCMOD_Pos)
7575
7576/****************** Bit definition for FSMC_BWTR3 register ******************/
7577#define FSMC_BWTR3_ADDSET_Pos (0U)
7578#define FSMC_BWTR3_ADDSET_Msk (0xFUL << FSMC_BWTR3_ADDSET_Pos)
7579#define FSMC_BWTR3_ADDSET FSMC_BWTR3_ADDSET_Msk
7580#define FSMC_BWTR3_ADDSET_0 (0x1UL << FSMC_BWTR3_ADDSET_Pos)
7581#define FSMC_BWTR3_ADDSET_1 (0x2UL << FSMC_BWTR3_ADDSET_Pos)
7582#define FSMC_BWTR3_ADDSET_2 (0x4UL << FSMC_BWTR3_ADDSET_Pos)
7583#define FSMC_BWTR3_ADDSET_3 (0x8UL << FSMC_BWTR3_ADDSET_Pos)
7584
7585#define FSMC_BWTR3_ADDHLD_Pos (4U)
7586#define FSMC_BWTR3_ADDHLD_Msk (0xFUL << FSMC_BWTR3_ADDHLD_Pos)
7587#define FSMC_BWTR3_ADDHLD FSMC_BWTR3_ADDHLD_Msk
7588#define FSMC_BWTR3_ADDHLD_0 (0x1UL << FSMC_BWTR3_ADDHLD_Pos)
7589#define FSMC_BWTR3_ADDHLD_1 (0x2UL << FSMC_BWTR3_ADDHLD_Pos)
7590#define FSMC_BWTR3_ADDHLD_2 (0x4UL << FSMC_BWTR3_ADDHLD_Pos)
7591#define FSMC_BWTR3_ADDHLD_3 (0x8UL << FSMC_BWTR3_ADDHLD_Pos)
7592
7593#define FSMC_BWTR3_DATAST_Pos (8U)
7594#define FSMC_BWTR3_DATAST_Msk (0xFFUL << FSMC_BWTR3_DATAST_Pos)
7595#define FSMC_BWTR3_DATAST FSMC_BWTR3_DATAST_Msk
7596#define FSMC_BWTR3_DATAST_0 (0x01UL << FSMC_BWTR3_DATAST_Pos)
7597#define FSMC_BWTR3_DATAST_1 (0x02UL << FSMC_BWTR3_DATAST_Pos)
7598#define FSMC_BWTR3_DATAST_2 (0x04UL << FSMC_BWTR3_DATAST_Pos)
7599#define FSMC_BWTR3_DATAST_3 (0x08UL << FSMC_BWTR3_DATAST_Pos)
7600#define FSMC_BWTR3_DATAST_4 (0x10UL << FSMC_BWTR3_DATAST_Pos)
7601#define FSMC_BWTR3_DATAST_5 (0x20UL << FSMC_BWTR3_DATAST_Pos)
7602#define FSMC_BWTR3_DATAST_6 (0x40UL << FSMC_BWTR3_DATAST_Pos)
7603#define FSMC_BWTR3_DATAST_7 (0x80UL << FSMC_BWTR3_DATAST_Pos)
7604
7605#define FSMC_BWTR3_BUSTURN_Pos (16U)
7606#define FSMC_BWTR3_BUSTURN_Msk (0xFUL << FSMC_BWTR3_BUSTURN_Pos)
7607#define FSMC_BWTR3_BUSTURN FSMC_BWTR3_BUSTURN_Msk
7608#define FSMC_BWTR3_BUSTURN_0 (0x1UL << FSMC_BWTR3_BUSTURN_Pos)
7609#define FSMC_BWTR3_BUSTURN_1 (0x2UL << FSMC_BWTR3_BUSTURN_Pos)
7610#define FSMC_BWTR3_BUSTURN_2 (0x4UL << FSMC_BWTR3_BUSTURN_Pos)
7611#define FSMC_BWTR3_BUSTURN_3 (0x8UL << FSMC_BWTR3_BUSTURN_Pos)
7612
7613#define FSMC_BWTR3_ACCMOD_Pos (28U)
7614#define FSMC_BWTR3_ACCMOD_Msk (0x3UL << FSMC_BWTR3_ACCMOD_Pos)
7615#define FSMC_BWTR3_ACCMOD FSMC_BWTR3_ACCMOD_Msk
7616#define FSMC_BWTR3_ACCMOD_0 (0x1UL << FSMC_BWTR3_ACCMOD_Pos)
7617#define FSMC_BWTR3_ACCMOD_1 (0x2UL << FSMC_BWTR3_ACCMOD_Pos)
7618
7619/****************** Bit definition for FSMC_BWTR4 register ******************/
7620#define FSMC_BWTR4_ADDSET_Pos (0U)
7621#define FSMC_BWTR4_ADDSET_Msk (0xFUL << FSMC_BWTR4_ADDSET_Pos)
7622#define FSMC_BWTR4_ADDSET FSMC_BWTR4_ADDSET_Msk
7623#define FSMC_BWTR4_ADDSET_0 (0x1UL << FSMC_BWTR4_ADDSET_Pos)
7624#define FSMC_BWTR4_ADDSET_1 (0x2UL << FSMC_BWTR4_ADDSET_Pos)
7625#define FSMC_BWTR4_ADDSET_2 (0x4UL << FSMC_BWTR4_ADDSET_Pos)
7626#define FSMC_BWTR4_ADDSET_3 (0x8UL << FSMC_BWTR4_ADDSET_Pos)
7627
7628#define FSMC_BWTR4_ADDHLD_Pos (4U)
7629#define FSMC_BWTR4_ADDHLD_Msk (0xFUL << FSMC_BWTR4_ADDHLD_Pos)
7630#define FSMC_BWTR4_ADDHLD FSMC_BWTR4_ADDHLD_Msk
7631#define FSMC_BWTR4_ADDHLD_0 (0x1UL << FSMC_BWTR4_ADDHLD_Pos)
7632#define FSMC_BWTR4_ADDHLD_1 (0x2UL << FSMC_BWTR4_ADDHLD_Pos)
7633#define FSMC_BWTR4_ADDHLD_2 (0x4UL << FSMC_BWTR4_ADDHLD_Pos)
7634#define FSMC_BWTR4_ADDHLD_3 (0x8UL << FSMC_BWTR4_ADDHLD_Pos)
7635
7636#define FSMC_BWTR4_DATAST_Pos (8U)
7637#define FSMC_BWTR4_DATAST_Msk (0xFFUL << FSMC_BWTR4_DATAST_Pos)
7638#define FSMC_BWTR4_DATAST FSMC_BWTR4_DATAST_Msk
7639#define FSMC_BWTR4_DATAST_0 0x00000100U
7640#define FSMC_BWTR4_DATAST_1 0x00000200U
7641#define FSMC_BWTR4_DATAST_2 0x00000400U
7642#define FSMC_BWTR4_DATAST_3 0x00000800U
7643#define FSMC_BWTR4_DATAST_4 0x00001000U
7644#define FSMC_BWTR4_DATAST_5 0x00002000U
7645#define FSMC_BWTR4_DATAST_6 0x00004000U
7646#define FSMC_BWTR4_DATAST_7 0x00008000U
7647
7648#define FSMC_BWTR4_BUSTURN_Pos (16U)
7649#define FSMC_BWTR4_BUSTURN_Msk (0xFUL << FSMC_BWTR4_BUSTURN_Pos)
7650#define FSMC_BWTR4_BUSTURN FSMC_BWTR4_BUSTURN_Msk
7651#define FSMC_BWTR4_BUSTURN_0 (0x1UL << FSMC_BWTR4_BUSTURN_Pos)
7652#define FSMC_BWTR4_BUSTURN_1 (0x2UL << FSMC_BWTR4_BUSTURN_Pos)
7653#define FSMC_BWTR4_BUSTURN_2 (0x4UL << FSMC_BWTR4_BUSTURN_Pos)
7654#define FSMC_BWTR4_BUSTURN_3 (0x8UL << FSMC_BWTR4_BUSTURN_Pos)
7655
7656#define FSMC_BWTR4_ACCMOD_Pos (28U)
7657#define FSMC_BWTR4_ACCMOD_Msk (0x3UL << FSMC_BWTR4_ACCMOD_Pos)
7658#define FSMC_BWTR4_ACCMOD FSMC_BWTR4_ACCMOD_Msk
7659#define FSMC_BWTR4_ACCMOD_0 (0x1UL << FSMC_BWTR4_ACCMOD_Pos)
7660#define FSMC_BWTR4_ACCMOD_1 (0x2UL << FSMC_BWTR4_ACCMOD_Pos)
7661
7662/******************************************************************************/
7663/* */
7664/* General Purpose I/O */
7665/* */
7666/******************************************************************************/
7667/****************** Bits definition for GPIO_MODER register *****************/
7668#define GPIO_MODER_MODER0_Pos (0U)
7669#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
7670#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
7671#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
7672#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
7673#define GPIO_MODER_MODER1_Pos (2U)
7674#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
7675#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
7676#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
7677#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
7678#define GPIO_MODER_MODER2_Pos (4U)
7679#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
7680#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
7681#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
7682#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
7683#define GPIO_MODER_MODER3_Pos (6U)
7684#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
7685#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
7686#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
7687#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
7688#define GPIO_MODER_MODER4_Pos (8U)
7689#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
7690#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
7691#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
7692#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
7693#define GPIO_MODER_MODER5_Pos (10U)
7694#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
7695#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
7696#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
7697#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
7698#define GPIO_MODER_MODER6_Pos (12U)
7699#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
7700#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
7701#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
7702#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
7703#define GPIO_MODER_MODER7_Pos (14U)
7704#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
7705#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
7706#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
7707#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
7708#define GPIO_MODER_MODER8_Pos (16U)
7709#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
7710#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
7711#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
7712#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
7713#define GPIO_MODER_MODER9_Pos (18U)
7714#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
7715#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
7716#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
7717#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
7718#define GPIO_MODER_MODER10_Pos (20U)
7719#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
7720#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
7721#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
7722#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
7723#define GPIO_MODER_MODER11_Pos (22U)
7724#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
7725#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
7726#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
7727#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
7728#define GPIO_MODER_MODER12_Pos (24U)
7729#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
7730#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
7731#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
7732#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
7733#define GPIO_MODER_MODER13_Pos (26U)
7734#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
7735#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
7736#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
7737#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
7738#define GPIO_MODER_MODER14_Pos (28U)
7739#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
7740#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
7741#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
7742#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
7743#define GPIO_MODER_MODER15_Pos (30U)
7744#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
7745#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
7746#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
7747#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
7748
7749
7750/****************** Bits definition for GPIO_OTYPER register ****************/
7751#define GPIO_OTYPER_OT0_Pos (0U)
7752#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
7753#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
7754#define GPIO_OTYPER_OT1_Pos (1U)
7755#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
7756#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
7757#define GPIO_OTYPER_OT2_Pos (2U)
7758#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
7759#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
7760#define GPIO_OTYPER_OT3_Pos (3U)
7761#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
7762#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
7763#define GPIO_OTYPER_OT4_Pos (4U)
7764#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
7765#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
7766#define GPIO_OTYPER_OT5_Pos (5U)
7767#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
7768#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
7769#define GPIO_OTYPER_OT6_Pos (6U)
7770#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
7771#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
7772#define GPIO_OTYPER_OT7_Pos (7U)
7773#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
7774#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
7775#define GPIO_OTYPER_OT8_Pos (8U)
7776#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
7777#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
7778#define GPIO_OTYPER_OT9_Pos (9U)
7779#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
7780#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
7781#define GPIO_OTYPER_OT10_Pos (10U)
7782#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
7783#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
7784#define GPIO_OTYPER_OT11_Pos (11U)
7785#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
7786#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
7787#define GPIO_OTYPER_OT12_Pos (12U)
7788#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
7789#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
7790#define GPIO_OTYPER_OT13_Pos (13U)
7791#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
7792#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
7793#define GPIO_OTYPER_OT14_Pos (14U)
7794#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
7795#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
7796#define GPIO_OTYPER_OT15_Pos (15U)
7797#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
7798#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
7799
7800/* Legacy defines */
7801#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
7802#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
7803#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
7804#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
7805#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
7806#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
7807#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
7808#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
7809#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
7810#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
7811#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
7812#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
7813#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
7814#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
7815#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
7816#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
7817
7818/****************** Bits definition for GPIO_OSPEEDR register ***************/
7819#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
7820#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
7821#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
7822#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
7823#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
7824#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
7825#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
7826#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
7827#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
7828#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
7829#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
7830#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
7831#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
7832#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
7833#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
7834#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
7835#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
7836#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
7837#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
7838#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
7839#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
7840#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
7841#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
7842#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
7843#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
7844#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
7845#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
7846#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
7847#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
7848#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
7849#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
7850#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
7851#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
7852#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
7853#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
7854#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
7855#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
7856#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
7857#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
7858#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
7859#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
7860#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
7861#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
7862#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
7863#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
7864#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
7865#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
7866#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
7867#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
7868#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
7869#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
7870#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
7871#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
7872#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
7873#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
7874#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
7875#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
7876#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
7877#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
7878#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
7879#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
7880#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
7881#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
7882#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
7883#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
7884#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
7885#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
7886#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
7887#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
7888#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
7889#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
7890#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
7891#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
7892#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
7893#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
7894#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
7895#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
7896#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
7897#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
7898#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
7899
7900/* Legacy defines */
7901#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
7902#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
7903#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
7904#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
7905#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
7906#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
7907#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
7908#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
7909#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
7910#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
7911#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
7912#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
7913#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
7914#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
7915#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
7916#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
7917#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
7918#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
7919#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
7920#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
7921#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
7922#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
7923#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
7924#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
7925#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
7926#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
7927#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
7928#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
7929#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
7930#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
7931#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
7932#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
7933#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
7934#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
7935#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
7936#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
7937#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
7938#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
7939#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
7940#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
7941#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
7942#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
7943#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
7944#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
7945#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
7946#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
7947#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
7948#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
7949
7950/****************** Bits definition for GPIO_PUPDR register *****************/
7951#define GPIO_PUPDR_PUPD0_Pos (0U)
7952#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
7953#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
7954#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
7955#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
7956#define GPIO_PUPDR_PUPD1_Pos (2U)
7957#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
7958#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
7959#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
7960#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
7961#define GPIO_PUPDR_PUPD2_Pos (4U)
7962#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
7963#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
7964#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
7965#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
7966#define GPIO_PUPDR_PUPD3_Pos (6U)
7967#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
7968#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
7969#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
7970#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
7971#define GPIO_PUPDR_PUPD4_Pos (8U)
7972#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
7973#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
7974#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
7975#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
7976#define GPIO_PUPDR_PUPD5_Pos (10U)
7977#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
7978#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
7979#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
7980#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
7981#define GPIO_PUPDR_PUPD6_Pos (12U)
7982#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
7983#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
7984#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
7985#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
7986#define GPIO_PUPDR_PUPD7_Pos (14U)
7987#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
7988#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
7989#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
7990#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
7991#define GPIO_PUPDR_PUPD8_Pos (16U)
7992#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
7993#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
7994#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
7995#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
7996#define GPIO_PUPDR_PUPD9_Pos (18U)
7997#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
7998#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
7999#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
8000#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
8001#define GPIO_PUPDR_PUPD10_Pos (20U)
8002#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
8003#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
8004#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
8005#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
8006#define GPIO_PUPDR_PUPD11_Pos (22U)
8007#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
8008#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
8009#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
8010#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
8011#define GPIO_PUPDR_PUPD12_Pos (24U)
8012#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
8013#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
8014#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
8015#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
8016#define GPIO_PUPDR_PUPD13_Pos (26U)
8017#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
8018#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
8019#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
8020#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
8021#define GPIO_PUPDR_PUPD14_Pos (28U)
8022#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
8023#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
8024#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
8025#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
8026#define GPIO_PUPDR_PUPD15_Pos (30U)
8027#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
8028#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
8029#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
8030#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
8031
8032/* Legacy defines */
8033#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
8034#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
8035#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
8036#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
8037#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
8038#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
8039#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
8040#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
8041#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
8042#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
8043#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
8044#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
8045#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
8046#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
8047#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
8048#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
8049#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
8050#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
8051#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
8052#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
8053#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
8054#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
8055#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
8056#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
8057#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
8058#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
8059#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
8060#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
8061#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
8062#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
8063#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
8064#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
8065#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
8066#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
8067#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
8068#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
8069#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
8070#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
8071#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
8072#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
8073#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
8074#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
8075#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
8076#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
8077#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
8078#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
8079#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
8080#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
8081
8082/****************** Bits definition for GPIO_IDR register *******************/
8083#define GPIO_IDR_ID0_Pos (0U)
8084#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
8085#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8086#define GPIO_IDR_ID1_Pos (1U)
8087#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
8088#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8089#define GPIO_IDR_ID2_Pos (2U)
8090#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
8091#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8092#define GPIO_IDR_ID3_Pos (3U)
8093#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
8094#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8095#define GPIO_IDR_ID4_Pos (4U)
8096#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
8097#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8098#define GPIO_IDR_ID5_Pos (5U)
8099#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
8100#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8101#define GPIO_IDR_ID6_Pos (6U)
8102#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
8103#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8104#define GPIO_IDR_ID7_Pos (7U)
8105#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
8106#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8107#define GPIO_IDR_ID8_Pos (8U)
8108#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
8109#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8110#define GPIO_IDR_ID9_Pos (9U)
8111#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
8112#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8113#define GPIO_IDR_ID10_Pos (10U)
8114#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
8115#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8116#define GPIO_IDR_ID11_Pos (11U)
8117#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
8118#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8119#define GPIO_IDR_ID12_Pos (12U)
8120#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
8121#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8122#define GPIO_IDR_ID13_Pos (13U)
8123#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
8124#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8125#define GPIO_IDR_ID14_Pos (14U)
8126#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
8127#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8128#define GPIO_IDR_ID15_Pos (15U)
8129#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
8130#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8131
8132/* Legacy defines */
8133#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8134#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8135#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8136#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8137#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8138#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8139#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8140#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
8141#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
8142#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
8143#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
8144#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
8145#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
8146#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
8147#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
8148#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
8149
8150/****************** Bits definition for GPIO_ODR register *******************/
8151#define GPIO_ODR_OD0_Pos (0U)
8152#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
8153#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8154#define GPIO_ODR_OD1_Pos (1U)
8155#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
8156#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8157#define GPIO_ODR_OD2_Pos (2U)
8158#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
8159#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8160#define GPIO_ODR_OD3_Pos (3U)
8161#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
8162#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8163#define GPIO_ODR_OD4_Pos (4U)
8164#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
8165#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8166#define GPIO_ODR_OD5_Pos (5U)
8167#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
8168#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8169#define GPIO_ODR_OD6_Pos (6U)
8170#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
8171#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8172#define GPIO_ODR_OD7_Pos (7U)
8173#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
8174#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8175#define GPIO_ODR_OD8_Pos (8U)
8176#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
8177#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8178#define GPIO_ODR_OD9_Pos (9U)
8179#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
8180#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8181#define GPIO_ODR_OD10_Pos (10U)
8182#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
8183#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8184#define GPIO_ODR_OD11_Pos (11U)
8185#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
8186#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8187#define GPIO_ODR_OD12_Pos (12U)
8188#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
8189#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8190#define GPIO_ODR_OD13_Pos (13U)
8191#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
8192#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8193#define GPIO_ODR_OD14_Pos (14U)
8194#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
8195#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8196#define GPIO_ODR_OD15_Pos (15U)
8197#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
8198#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8199/* Legacy defines */
8200#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8201#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8202#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8203#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8204#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8205#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8206#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8207#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8208#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8209#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8210#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8211#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8212#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8213#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8214#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8215#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8216
8217/****************** Bits definition for GPIO_BSRR register ******************/
8218#define GPIO_BSRR_BS0_Pos (0U)
8219#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
8220#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8221#define GPIO_BSRR_BS1_Pos (1U)
8222#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
8223#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8224#define GPIO_BSRR_BS2_Pos (2U)
8225#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
8226#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8227#define GPIO_BSRR_BS3_Pos (3U)
8228#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
8229#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8230#define GPIO_BSRR_BS4_Pos (4U)
8231#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
8232#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8233#define GPIO_BSRR_BS5_Pos (5U)
8234#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
8235#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8236#define GPIO_BSRR_BS6_Pos (6U)
8237#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
8238#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8239#define GPIO_BSRR_BS7_Pos (7U)
8240#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
8241#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8242#define GPIO_BSRR_BS8_Pos (8U)
8243#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
8244#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8245#define GPIO_BSRR_BS9_Pos (9U)
8246#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
8247#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8248#define GPIO_BSRR_BS10_Pos (10U)
8249#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
8250#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8251#define GPIO_BSRR_BS11_Pos (11U)
8252#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
8253#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8254#define GPIO_BSRR_BS12_Pos (12U)
8255#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
8256#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8257#define GPIO_BSRR_BS13_Pos (13U)
8258#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
8259#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8260#define GPIO_BSRR_BS14_Pos (14U)
8261#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
8262#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8263#define GPIO_BSRR_BS15_Pos (15U)
8264#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
8265#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8266#define GPIO_BSRR_BR0_Pos (16U)
8267#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
8268#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8269#define GPIO_BSRR_BR1_Pos (17U)
8270#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
8271#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8272#define GPIO_BSRR_BR2_Pos (18U)
8273#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
8274#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8275#define GPIO_BSRR_BR3_Pos (19U)
8276#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
8277#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8278#define GPIO_BSRR_BR4_Pos (20U)
8279#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
8280#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8281#define GPIO_BSRR_BR5_Pos (21U)
8282#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
8283#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8284#define GPIO_BSRR_BR6_Pos (22U)
8285#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
8286#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8287#define GPIO_BSRR_BR7_Pos (23U)
8288#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
8289#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8290#define GPIO_BSRR_BR8_Pos (24U)
8291#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
8292#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8293#define GPIO_BSRR_BR9_Pos (25U)
8294#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
8295#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8296#define GPIO_BSRR_BR10_Pos (26U)
8297#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
8298#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8299#define GPIO_BSRR_BR11_Pos (27U)
8300#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
8301#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8302#define GPIO_BSRR_BR12_Pos (28U)
8303#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
8304#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8305#define GPIO_BSRR_BR13_Pos (29U)
8306#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
8307#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8308#define GPIO_BSRR_BR14_Pos (30U)
8309#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
8310#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8311#define GPIO_BSRR_BR15_Pos (31U)
8312#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
8313#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8314
8315/* Legacy defines */
8316#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8317#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8318#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8319#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8320#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8321#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8322#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8323#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8324#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8325#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8326#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8327#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8328#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8329#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8330#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8331#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8332#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8333#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8334#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8335#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8336#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8337#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8338#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8339#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8340#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8341#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8342#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8343#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8344#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8345#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8346#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8347#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8348#define GPIO_BRR_BR0 GPIO_BSRR_BR0
8349#define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
8350#define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
8351#define GPIO_BRR_BR1 GPIO_BSRR_BR1
8352#define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
8353#define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
8354#define GPIO_BRR_BR2 GPIO_BSRR_BR2
8355#define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
8356#define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
8357#define GPIO_BRR_BR3 GPIO_BSRR_BR3
8358#define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
8359#define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
8360#define GPIO_BRR_BR4 GPIO_BSRR_BR4
8361#define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
8362#define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
8363#define GPIO_BRR_BR5 GPIO_BSRR_BR5
8364#define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
8365#define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
8366#define GPIO_BRR_BR6 GPIO_BSRR_BR6
8367#define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
8368#define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
8369#define GPIO_BRR_BR7 GPIO_BSRR_BR7
8370#define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
8371#define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
8372#define GPIO_BRR_BR8 GPIO_BSRR_BR8
8373#define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
8374#define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
8375#define GPIO_BRR_BR9 GPIO_BSRR_BR9
8376#define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
8377#define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
8378#define GPIO_BRR_BR10 GPIO_BSRR_BR10
8379#define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
8380#define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
8381#define GPIO_BRR_BR11 GPIO_BSRR_BR11
8382#define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
8383#define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
8384#define GPIO_BRR_BR12 GPIO_BSRR_BR12
8385#define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
8386#define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
8387#define GPIO_BRR_BR13 GPIO_BSRR_BR13
8388#define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
8389#define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
8390#define GPIO_BRR_BR14 GPIO_BSRR_BR14
8391#define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
8392#define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
8393#define GPIO_BRR_BR15 GPIO_BSRR_BR15
8394#define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
8395#define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
8396/****************** Bit definition for GPIO_LCKR register *********************/
8397#define GPIO_LCKR_LCK0_Pos (0U)
8398#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
8399#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8400#define GPIO_LCKR_LCK1_Pos (1U)
8401#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
8402#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8403#define GPIO_LCKR_LCK2_Pos (2U)
8404#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
8405#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8406#define GPIO_LCKR_LCK3_Pos (3U)
8407#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
8408#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8409#define GPIO_LCKR_LCK4_Pos (4U)
8410#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
8411#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8412#define GPIO_LCKR_LCK5_Pos (5U)
8413#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
8414#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8415#define GPIO_LCKR_LCK6_Pos (6U)
8416#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
8417#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8418#define GPIO_LCKR_LCK7_Pos (7U)
8419#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
8420#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8421#define GPIO_LCKR_LCK8_Pos (8U)
8422#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
8423#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8424#define GPIO_LCKR_LCK9_Pos (9U)
8425#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
8426#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8427#define GPIO_LCKR_LCK10_Pos (10U)
8428#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
8429#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8430#define GPIO_LCKR_LCK11_Pos (11U)
8431#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
8432#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8433#define GPIO_LCKR_LCK12_Pos (12U)
8434#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
8435#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8436#define GPIO_LCKR_LCK13_Pos (13U)
8437#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
8438#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8439#define GPIO_LCKR_LCK14_Pos (14U)
8440#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
8441#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8442#define GPIO_LCKR_LCK15_Pos (15U)
8443#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
8444#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8445#define GPIO_LCKR_LCKK_Pos (16U)
8446#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
8447#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8448/****************** Bit definition for GPIO_AFRL register *********************/
8449#define GPIO_AFRL_AFSEL0_Pos (0U)
8450#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
8451#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8452#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
8453#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
8454#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
8455#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
8456#define GPIO_AFRL_AFSEL1_Pos (4U)
8457#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
8458#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8459#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
8460#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
8461#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
8462#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
8463#define GPIO_AFRL_AFSEL2_Pos (8U)
8464#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
8465#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8466#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
8467#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
8468#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
8469#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
8470#define GPIO_AFRL_AFSEL3_Pos (12U)
8471#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
8472#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8473#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
8474#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
8475#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
8476#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
8477#define GPIO_AFRL_AFSEL4_Pos (16U)
8478#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
8479#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8480#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
8481#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
8482#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
8483#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
8484#define GPIO_AFRL_AFSEL5_Pos (20U)
8485#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
8486#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8487#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
8488#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
8489#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
8490#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
8491#define GPIO_AFRL_AFSEL6_Pos (24U)
8492#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
8493#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
8494#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
8495#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
8496#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
8497#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
8498#define GPIO_AFRL_AFSEL7_Pos (28U)
8499#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
8500#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
8501#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
8502#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
8503#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
8504#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
8505
8506/* Legacy defines */
8507#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
8508#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
8509#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
8510#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
8511#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
8512#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
8513#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
8514#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
8515#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
8516#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
8517#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
8518#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
8519#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
8520#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
8521#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
8522#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
8523#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
8524#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
8525#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
8526#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
8527#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
8528#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
8529#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
8530#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
8531#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
8532#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
8533#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
8534#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
8535#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
8536#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
8537#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
8538#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
8539#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
8540#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
8541#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
8542#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
8543#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
8544#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
8545#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
8546#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
8547
8548/****************** Bit definition for GPIO_AFRH register *********************/
8549#define GPIO_AFRH_AFSEL8_Pos (0U)
8550#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
8551#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
8552#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
8553#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
8554#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
8555#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
8556#define GPIO_AFRH_AFSEL9_Pos (4U)
8557#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
8558#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
8559#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
8560#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
8561#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
8562#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
8563#define GPIO_AFRH_AFSEL10_Pos (8U)
8564#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
8565#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
8566#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
8567#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
8568#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
8569#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
8570#define GPIO_AFRH_AFSEL11_Pos (12U)
8571#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
8572#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
8573#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
8574#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
8575#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
8576#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
8577#define GPIO_AFRH_AFSEL12_Pos (16U)
8578#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
8579#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
8580#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
8581#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
8582#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
8583#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
8584#define GPIO_AFRH_AFSEL13_Pos (20U)
8585#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
8586#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
8587#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
8588#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
8589#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
8590#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
8591#define GPIO_AFRH_AFSEL14_Pos (24U)
8592#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
8593#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
8594#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
8595#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
8596#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
8597#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
8598#define GPIO_AFRH_AFSEL15_Pos (28U)
8599#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
8600#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
8601#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
8602#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
8603#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
8604#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
8605
8606/* Legacy defines */
8607#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
8608#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
8609#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
8610#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
8611#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
8612#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
8613#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
8614#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
8615#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
8616#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
8617#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
8618#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
8619#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
8620#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
8621#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
8622#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
8623#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
8624#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
8625#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
8626#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
8627#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
8628#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
8629#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
8630#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
8631#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
8632#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
8633#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
8634#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
8635#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
8636#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
8637#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
8638#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
8639#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
8640#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
8641#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
8642#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
8643#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
8644#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
8645#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
8646#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
8647
8648
8649/******************************************************************************/
8650/* */
8651/* Inter-integrated Circuit Interface */
8652/* */
8653/******************************************************************************/
8654/******************* Bit definition for I2C_CR1 register ********************/
8655#define I2C_CR1_PE_Pos (0U)
8656#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
8657#define I2C_CR1_PE I2C_CR1_PE_Msk
8658#define I2C_CR1_SMBUS_Pos (1U)
8659#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
8660#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
8661#define I2C_CR1_SMBTYPE_Pos (3U)
8662#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
8663#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
8664#define I2C_CR1_ENARP_Pos (4U)
8665#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
8666#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
8667#define I2C_CR1_ENPEC_Pos (5U)
8668#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
8669#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
8670#define I2C_CR1_ENGC_Pos (6U)
8671#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
8672#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
8673#define I2C_CR1_NOSTRETCH_Pos (7U)
8674#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
8675#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
8676#define I2C_CR1_START_Pos (8U)
8677#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
8678#define I2C_CR1_START I2C_CR1_START_Msk
8679#define I2C_CR1_STOP_Pos (9U)
8680#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
8681#define I2C_CR1_STOP I2C_CR1_STOP_Msk
8682#define I2C_CR1_ACK_Pos (10U)
8683#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
8684#define I2C_CR1_ACK I2C_CR1_ACK_Msk
8685#define I2C_CR1_POS_Pos (11U)
8686#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
8687#define I2C_CR1_POS I2C_CR1_POS_Msk
8688#define I2C_CR1_PEC_Pos (12U)
8689#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
8690#define I2C_CR1_PEC I2C_CR1_PEC_Msk
8691#define I2C_CR1_ALERT_Pos (13U)
8692#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
8693#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
8694#define I2C_CR1_SWRST_Pos (15U)
8695#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
8696#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
8697
8698/******************* Bit definition for I2C_CR2 register ********************/
8699#define I2C_CR2_FREQ_Pos (0U)
8700#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
8701#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
8702#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
8703#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
8704#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
8705#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
8706#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
8707#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
8708
8709#define I2C_CR2_ITERREN_Pos (8U)
8710#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
8711#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
8712#define I2C_CR2_ITEVTEN_Pos (9U)
8713#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
8714#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
8715#define I2C_CR2_ITBUFEN_Pos (10U)
8716#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
8717#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
8718#define I2C_CR2_DMAEN_Pos (11U)
8719#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
8720#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
8721#define I2C_CR2_LAST_Pos (12U)
8722#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
8723#define I2C_CR2_LAST I2C_CR2_LAST_Msk
8724
8725/******************* Bit definition for I2C_OAR1 register *******************/
8726#define I2C_OAR1_ADD1_7 0x000000FEU
8727#define I2C_OAR1_ADD8_9 0x00000300U
8728
8729#define I2C_OAR1_ADD0_Pos (0U)
8730#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
8731#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
8732#define I2C_OAR1_ADD1_Pos (1U)
8733#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
8734#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
8735#define I2C_OAR1_ADD2_Pos (2U)
8736#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
8737#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
8738#define I2C_OAR1_ADD3_Pos (3U)
8739#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
8740#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
8741#define I2C_OAR1_ADD4_Pos (4U)
8742#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
8743#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
8744#define I2C_OAR1_ADD5_Pos (5U)
8745#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
8746#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
8747#define I2C_OAR1_ADD6_Pos (6U)
8748#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
8749#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
8750#define I2C_OAR1_ADD7_Pos (7U)
8751#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
8752#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
8753#define I2C_OAR1_ADD8_Pos (8U)
8754#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
8755#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
8756#define I2C_OAR1_ADD9_Pos (9U)
8757#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
8758#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
8759
8760#define I2C_OAR1_ADDMODE_Pos (15U)
8761#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
8762#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
8763
8764/******************* Bit definition for I2C_OAR2 register *******************/
8765#define I2C_OAR2_ENDUAL_Pos (0U)
8766#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
8767#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
8768#define I2C_OAR2_ADD2_Pos (1U)
8769#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
8770#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
8771
8772/******************** Bit definition for I2C_DR register ********************/
8773#define I2C_DR_DR_Pos (0U)
8774#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
8775#define I2C_DR_DR I2C_DR_DR_Msk
8776
8777/******************* Bit definition for I2C_SR1 register ********************/
8778#define I2C_SR1_SB_Pos (0U)
8779#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
8780#define I2C_SR1_SB I2C_SR1_SB_Msk
8781#define I2C_SR1_ADDR_Pos (1U)
8782#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
8783#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
8784#define I2C_SR1_BTF_Pos (2U)
8785#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
8786#define I2C_SR1_BTF I2C_SR1_BTF_Msk
8787#define I2C_SR1_ADD10_Pos (3U)
8788#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
8789#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
8790#define I2C_SR1_STOPF_Pos (4U)
8791#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
8792#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
8793#define I2C_SR1_RXNE_Pos (6U)
8794#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
8795#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
8796#define I2C_SR1_TXE_Pos (7U)
8797#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
8798#define I2C_SR1_TXE I2C_SR1_TXE_Msk
8799#define I2C_SR1_BERR_Pos (8U)
8800#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
8801#define I2C_SR1_BERR I2C_SR1_BERR_Msk
8802#define I2C_SR1_ARLO_Pos (9U)
8803#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
8804#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
8805#define I2C_SR1_AF_Pos (10U)
8806#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
8807#define I2C_SR1_AF I2C_SR1_AF_Msk
8808#define I2C_SR1_OVR_Pos (11U)
8809#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
8810#define I2C_SR1_OVR I2C_SR1_OVR_Msk
8811#define I2C_SR1_PECERR_Pos (12U)
8812#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
8813#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
8814#define I2C_SR1_TIMEOUT_Pos (14U)
8815#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
8816#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
8817#define I2C_SR1_SMBALERT_Pos (15U)
8818#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
8819#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
8820
8821/******************* Bit definition for I2C_SR2 register ********************/
8822#define I2C_SR2_MSL_Pos (0U)
8823#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
8824#define I2C_SR2_MSL I2C_SR2_MSL_Msk
8825#define I2C_SR2_BUSY_Pos (1U)
8826#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
8827#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
8828#define I2C_SR2_TRA_Pos (2U)
8829#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
8830#define I2C_SR2_TRA I2C_SR2_TRA_Msk
8831#define I2C_SR2_GENCALL_Pos (4U)
8832#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
8833#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
8834#define I2C_SR2_SMBDEFAULT_Pos (5U)
8835#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
8836#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
8837#define I2C_SR2_SMBHOST_Pos (6U)
8838#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
8839#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
8840#define I2C_SR2_DUALF_Pos (7U)
8841#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
8842#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
8843#define I2C_SR2_PEC_Pos (8U)
8844#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
8845#define I2C_SR2_PEC I2C_SR2_PEC_Msk
8846
8847/******************* Bit definition for I2C_CCR register ********************/
8848#define I2C_CCR_CCR_Pos (0U)
8849#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
8850#define I2C_CCR_CCR I2C_CCR_CCR_Msk
8851#define I2C_CCR_DUTY_Pos (14U)
8852#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
8853#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
8854#define I2C_CCR_FS_Pos (15U)
8855#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
8856#define I2C_CCR_FS I2C_CCR_FS_Msk
8857
8858/****************** Bit definition for I2C_TRISE register *******************/
8859#define I2C_TRISE_TRISE_Pos (0U)
8860#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
8861#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
8862
8863/****************** Bit definition for I2C_FLTR register *******************/
8864#define I2C_FLTR_DNF_Pos (0U)
8865#define I2C_FLTR_DNF_Msk (0xFUL << I2C_FLTR_DNF_Pos)
8866#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk
8867#define I2C_FLTR_ANOFF_Pos (4U)
8868#define I2C_FLTR_ANOFF_Msk (0x1UL << I2C_FLTR_ANOFF_Pos)
8869#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk
8870
8871/******************************************************************************/
8872/* */
8873/* Fast Mode Plus Inter-integrated Circuit Interface (I2C) */
8874/* */
8875/******************************************************************************/
8876/******************* Bit definition for I2C_CR1 register *******************/
8877#define FMPI2C_CR1_PE_Pos (0U)
8878#define FMPI2C_CR1_PE_Msk (0x1UL << FMPI2C_CR1_PE_Pos)
8879#define FMPI2C_CR1_PE FMPI2C_CR1_PE_Msk
8880#define FMPI2C_CR1_TXIE_Pos (1U)
8881#define FMPI2C_CR1_TXIE_Msk (0x1UL << FMPI2C_CR1_TXIE_Pos)
8882#define FMPI2C_CR1_TXIE FMPI2C_CR1_TXIE_Msk
8883#define FMPI2C_CR1_RXIE_Pos (2U)
8884#define FMPI2C_CR1_RXIE_Msk (0x1UL << FMPI2C_CR1_RXIE_Pos)
8885#define FMPI2C_CR1_RXIE FMPI2C_CR1_RXIE_Msk
8886#define FMPI2C_CR1_ADDRIE_Pos (3U)
8887#define FMPI2C_CR1_ADDRIE_Msk (0x1UL << FMPI2C_CR1_ADDRIE_Pos)
8888#define FMPI2C_CR1_ADDRIE FMPI2C_CR1_ADDRIE_Msk
8889#define FMPI2C_CR1_NACKIE_Pos (4U)
8890#define FMPI2C_CR1_NACKIE_Msk (0x1UL << FMPI2C_CR1_NACKIE_Pos)
8891#define FMPI2C_CR1_NACKIE FMPI2C_CR1_NACKIE_Msk
8892#define FMPI2C_CR1_STOPIE_Pos (5U)
8893#define FMPI2C_CR1_STOPIE_Msk (0x1UL << FMPI2C_CR1_STOPIE_Pos)
8894#define FMPI2C_CR1_STOPIE FMPI2C_CR1_STOPIE_Msk
8895#define FMPI2C_CR1_TCIE_Pos (6U)
8896#define FMPI2C_CR1_TCIE_Msk (0x1UL << FMPI2C_CR1_TCIE_Pos)
8897#define FMPI2C_CR1_TCIE FMPI2C_CR1_TCIE_Msk
8898#define FMPI2C_CR1_ERRIE_Pos (7U)
8899#define FMPI2C_CR1_ERRIE_Msk (0x1UL << FMPI2C_CR1_ERRIE_Pos)
8900#define FMPI2C_CR1_ERRIE FMPI2C_CR1_ERRIE_Msk
8901#define FMPI2C_CR1_DNF_Pos (8U)
8902#define FMPI2C_CR1_DNF_Msk (0xFUL << FMPI2C_CR1_DNF_Pos)
8903#define FMPI2C_CR1_DNF FMPI2C_CR1_DNF_Msk
8904#define FMPI2C_CR1_ANFOFF_Pos (12U)
8905#define FMPI2C_CR1_ANFOFF_Msk (0x1UL << FMPI2C_CR1_ANFOFF_Pos)
8906#define FMPI2C_CR1_ANFOFF FMPI2C_CR1_ANFOFF_Msk
8907#define FMPI2C_CR1_TXDMAEN_Pos (14U)
8908#define FMPI2C_CR1_TXDMAEN_Msk (0x1UL << FMPI2C_CR1_TXDMAEN_Pos)
8909#define FMPI2C_CR1_TXDMAEN FMPI2C_CR1_TXDMAEN_Msk
8910#define FMPI2C_CR1_RXDMAEN_Pos (15U)
8911#define FMPI2C_CR1_RXDMAEN_Msk (0x1UL << FMPI2C_CR1_RXDMAEN_Pos)
8912#define FMPI2C_CR1_RXDMAEN FMPI2C_CR1_RXDMAEN_Msk
8913#define FMPI2C_CR1_SBC_Pos (16U)
8914#define FMPI2C_CR1_SBC_Msk (0x1UL << FMPI2C_CR1_SBC_Pos)
8915#define FMPI2C_CR1_SBC FMPI2C_CR1_SBC_Msk
8916#define FMPI2C_CR1_NOSTRETCH_Pos (17U)
8917#define FMPI2C_CR1_NOSTRETCH_Msk (0x1UL << FMPI2C_CR1_NOSTRETCH_Pos)
8918#define FMPI2C_CR1_NOSTRETCH FMPI2C_CR1_NOSTRETCH_Msk
8919#define FMPI2C_CR1_GCEN_Pos (19U)
8920#define FMPI2C_CR1_GCEN_Msk (0x1UL << FMPI2C_CR1_GCEN_Pos)
8921#define FMPI2C_CR1_GCEN FMPI2C_CR1_GCEN_Msk
8922#define FMPI2C_CR1_SMBHEN_Pos (20U)
8923#define FMPI2C_CR1_SMBHEN_Msk (0x1UL << FMPI2C_CR1_SMBHEN_Pos)
8924#define FMPI2C_CR1_SMBHEN FMPI2C_CR1_SMBHEN_Msk
8925#define FMPI2C_CR1_SMBDEN_Pos (21U)
8926#define FMPI2C_CR1_SMBDEN_Msk (0x1UL << FMPI2C_CR1_SMBDEN_Pos)
8927#define FMPI2C_CR1_SMBDEN FMPI2C_CR1_SMBDEN_Msk
8928#define FMPI2C_CR1_ALERTEN_Pos (22U)
8929#define FMPI2C_CR1_ALERTEN_Msk (0x1UL << FMPI2C_CR1_ALERTEN_Pos)
8930#define FMPI2C_CR1_ALERTEN FMPI2C_CR1_ALERTEN_Msk
8931#define FMPI2C_CR1_PECEN_Pos (23U)
8932#define FMPI2C_CR1_PECEN_Msk (0x1UL << FMPI2C_CR1_PECEN_Pos)
8933#define FMPI2C_CR1_PECEN FMPI2C_CR1_PECEN_Msk
8934
8935/* Legacy Defines */
8936#define FMPI2C_CR1_DFN_Pos FMPI2C_CR1_DNF_Pos
8937#define FMPI2C_CR1_DFN_Msk FMPI2C_CR1_DNF_Msk
8938#define FMPI2C_CR1_DFN FMPI2C_CR1_DNF
8939/****************** Bit definition for I2C_CR2 register ********************/
8940#define FMPI2C_CR2_SADD_Pos (0U)
8941#define FMPI2C_CR2_SADD_Msk (0x3FFUL << FMPI2C_CR2_SADD_Pos)
8942#define FMPI2C_CR2_SADD FMPI2C_CR2_SADD_Msk
8943#define FMPI2C_CR2_RD_WRN_Pos (10U)
8944#define FMPI2C_CR2_RD_WRN_Msk (0x1UL << FMPI2C_CR2_RD_WRN_Pos)
8945#define FMPI2C_CR2_RD_WRN FMPI2C_CR2_RD_WRN_Msk
8946#define FMPI2C_CR2_ADD10_Pos (11U)
8947#define FMPI2C_CR2_ADD10_Msk (0x1UL << FMPI2C_CR2_ADD10_Pos)
8948#define FMPI2C_CR2_ADD10 FMPI2C_CR2_ADD10_Msk
8949#define FMPI2C_CR2_HEAD10R_Pos (12U)
8950#define FMPI2C_CR2_HEAD10R_Msk (0x1UL << FMPI2C_CR2_HEAD10R_Pos)
8951#define FMPI2C_CR2_HEAD10R FMPI2C_CR2_HEAD10R_Msk
8952#define FMPI2C_CR2_START_Pos (13U)
8953#define FMPI2C_CR2_START_Msk (0x1UL << FMPI2C_CR2_START_Pos)
8954#define FMPI2C_CR2_START FMPI2C_CR2_START_Msk
8955#define FMPI2C_CR2_STOP_Pos (14U)
8956#define FMPI2C_CR2_STOP_Msk (0x1UL << FMPI2C_CR2_STOP_Pos)
8957#define FMPI2C_CR2_STOP FMPI2C_CR2_STOP_Msk
8958#define FMPI2C_CR2_NACK_Pos (15U)
8959#define FMPI2C_CR2_NACK_Msk (0x1UL << FMPI2C_CR2_NACK_Pos)
8960#define FMPI2C_CR2_NACK FMPI2C_CR2_NACK_Msk
8961#define FMPI2C_CR2_NBYTES_Pos (16U)
8962#define FMPI2C_CR2_NBYTES_Msk (0xFFUL << FMPI2C_CR2_NBYTES_Pos)
8963#define FMPI2C_CR2_NBYTES FMPI2C_CR2_NBYTES_Msk
8964#define FMPI2C_CR2_RELOAD_Pos (24U)
8965#define FMPI2C_CR2_RELOAD_Msk (0x1UL << FMPI2C_CR2_RELOAD_Pos)
8966#define FMPI2C_CR2_RELOAD FMPI2C_CR2_RELOAD_Msk
8967#define FMPI2C_CR2_AUTOEND_Pos (25U)
8968#define FMPI2C_CR2_AUTOEND_Msk (0x1UL << FMPI2C_CR2_AUTOEND_Pos)
8969#define FMPI2C_CR2_AUTOEND FMPI2C_CR2_AUTOEND_Msk
8970#define FMPI2C_CR2_PECBYTE_Pos (26U)
8971#define FMPI2C_CR2_PECBYTE_Msk (0x1UL << FMPI2C_CR2_PECBYTE_Pos)
8972#define FMPI2C_CR2_PECBYTE FMPI2C_CR2_PECBYTE_Msk
8973
8974/******************* Bit definition for I2C_OAR1 register ******************/
8975#define FMPI2C_OAR1_OA1_Pos (0U)
8976#define FMPI2C_OAR1_OA1_Msk (0x3FFUL << FMPI2C_OAR1_OA1_Pos)
8977#define FMPI2C_OAR1_OA1 FMPI2C_OAR1_OA1_Msk
8978#define FMPI2C_OAR1_OA1MODE_Pos (10U)
8979#define FMPI2C_OAR1_OA1MODE_Msk (0x1UL << FMPI2C_OAR1_OA1MODE_Pos)
8980#define FMPI2C_OAR1_OA1MODE FMPI2C_OAR1_OA1MODE_Msk
8981#define FMPI2C_OAR1_OA1EN_Pos (15U)
8982#define FMPI2C_OAR1_OA1EN_Msk (0x1UL << FMPI2C_OAR1_OA1EN_Pos)
8983#define FMPI2C_OAR1_OA1EN FMPI2C_OAR1_OA1EN_Msk
8984
8985/******************* Bit definition for I2C_OAR2 register ******************/
8986#define FMPI2C_OAR2_OA2_Pos (1U)
8987#define FMPI2C_OAR2_OA2_Msk (0x7FUL << FMPI2C_OAR2_OA2_Pos)
8988#define FMPI2C_OAR2_OA2 FMPI2C_OAR2_OA2_Msk
8989#define FMPI2C_OAR2_OA2MSK_Pos (8U)
8990#define FMPI2C_OAR2_OA2MSK_Msk (0x7UL << FMPI2C_OAR2_OA2MSK_Pos)
8991#define FMPI2C_OAR2_OA2MSK FMPI2C_OAR2_OA2MSK_Msk
8992#define FMPI2C_OAR2_OA2EN_Pos (15U)
8993#define FMPI2C_OAR2_OA2EN_Msk (0x1UL << FMPI2C_OAR2_OA2EN_Pos)
8994#define FMPI2C_OAR2_OA2EN FMPI2C_OAR2_OA2EN_Msk
8995
8996/******************* Bit definition for I2C_TIMINGR register *******************/
8997#define FMPI2C_TIMINGR_SCLL_Pos (0U)
8998#define FMPI2C_TIMINGR_SCLL_Msk (0xFFUL << FMPI2C_TIMINGR_SCLL_Pos)
8999#define FMPI2C_TIMINGR_SCLL FMPI2C_TIMINGR_SCLL_Msk
9000#define FMPI2C_TIMINGR_SCLH_Pos (8U)
9001#define FMPI2C_TIMINGR_SCLH_Msk (0xFFUL << FMPI2C_TIMINGR_SCLH_Pos)
9002#define FMPI2C_TIMINGR_SCLH FMPI2C_TIMINGR_SCLH_Msk
9003#define FMPI2C_TIMINGR_SDADEL_Pos (16U)
9004#define FMPI2C_TIMINGR_SDADEL_Msk (0xFUL << FMPI2C_TIMINGR_SDADEL_Pos)
9005#define FMPI2C_TIMINGR_SDADEL FMPI2C_TIMINGR_SDADEL_Msk
9006#define FMPI2C_TIMINGR_SCLDEL_Pos (20U)
9007#define FMPI2C_TIMINGR_SCLDEL_Msk (0xFUL << FMPI2C_TIMINGR_SCLDEL_Pos)
9008#define FMPI2C_TIMINGR_SCLDEL FMPI2C_TIMINGR_SCLDEL_Msk
9009#define FMPI2C_TIMINGR_PRESC_Pos (28U)
9010#define FMPI2C_TIMINGR_PRESC_Msk (0xFUL << FMPI2C_TIMINGR_PRESC_Pos)
9011#define FMPI2C_TIMINGR_PRESC FMPI2C_TIMINGR_PRESC_Msk
9012
9013/******************* Bit definition for I2C_TIMEOUTR register *******************/
9014#define FMPI2C_TIMEOUTR_TIMEOUTA_Pos (0U)
9015#define FMPI2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTA_Pos)
9016#define FMPI2C_TIMEOUTR_TIMEOUTA FMPI2C_TIMEOUTR_TIMEOUTA_Msk
9017#define FMPI2C_TIMEOUTR_TIDLE_Pos (12U)
9018#define FMPI2C_TIMEOUTR_TIDLE_Msk (0x1UL << FMPI2C_TIMEOUTR_TIDLE_Pos)
9019#define FMPI2C_TIMEOUTR_TIDLE FMPI2C_TIMEOUTR_TIDLE_Msk
9020#define FMPI2C_TIMEOUTR_TIMOUTEN_Pos (15U)
9021#define FMPI2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << FMPI2C_TIMEOUTR_TIMOUTEN_Pos)
9022#define FMPI2C_TIMEOUTR_TIMOUTEN FMPI2C_TIMEOUTR_TIMOUTEN_Msk
9023#define FMPI2C_TIMEOUTR_TIMEOUTB_Pos (16U)
9024#define FMPI2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << FMPI2C_TIMEOUTR_TIMEOUTB_Pos)
9025#define FMPI2C_TIMEOUTR_TIMEOUTB FMPI2C_TIMEOUTR_TIMEOUTB_Msk
9026#define FMPI2C_TIMEOUTR_TEXTEN_Pos (31U)
9027#define FMPI2C_TIMEOUTR_TEXTEN_Msk (0x1UL << FMPI2C_TIMEOUTR_TEXTEN_Pos)
9028#define FMPI2C_TIMEOUTR_TEXTEN FMPI2C_TIMEOUTR_TEXTEN_Msk
9029
9030/****************** Bit definition for I2C_ISR register *********************/
9031#define FMPI2C_ISR_TXE_Pos (0U)
9032#define FMPI2C_ISR_TXE_Msk (0x1UL << FMPI2C_ISR_TXE_Pos)
9033#define FMPI2C_ISR_TXE FMPI2C_ISR_TXE_Msk
9034#define FMPI2C_ISR_TXIS_Pos (1U)
9035#define FMPI2C_ISR_TXIS_Msk (0x1UL << FMPI2C_ISR_TXIS_Pos)
9036#define FMPI2C_ISR_TXIS FMPI2C_ISR_TXIS_Msk
9037#define FMPI2C_ISR_RXNE_Pos (2U)
9038#define FMPI2C_ISR_RXNE_Msk (0x1UL << FMPI2C_ISR_RXNE_Pos)
9039#define FMPI2C_ISR_RXNE FMPI2C_ISR_RXNE_Msk
9040#define FMPI2C_ISR_ADDR_Pos (3U)
9041#define FMPI2C_ISR_ADDR_Msk (0x1UL << FMPI2C_ISR_ADDR_Pos)
9042#define FMPI2C_ISR_ADDR FMPI2C_ISR_ADDR_Msk
9043#define FMPI2C_ISR_NACKF_Pos (4U)
9044#define FMPI2C_ISR_NACKF_Msk (0x1UL << FMPI2C_ISR_NACKF_Pos)
9045#define FMPI2C_ISR_NACKF FMPI2C_ISR_NACKF_Msk
9046#define FMPI2C_ISR_STOPF_Pos (5U)
9047#define FMPI2C_ISR_STOPF_Msk (0x1UL << FMPI2C_ISR_STOPF_Pos)
9048#define FMPI2C_ISR_STOPF FMPI2C_ISR_STOPF_Msk
9049#define FMPI2C_ISR_TC_Pos (6U)
9050#define FMPI2C_ISR_TC_Msk (0x1UL << FMPI2C_ISR_TC_Pos)
9051#define FMPI2C_ISR_TC FMPI2C_ISR_TC_Msk
9052#define FMPI2C_ISR_TCR_Pos (7U)
9053#define FMPI2C_ISR_TCR_Msk (0x1UL << FMPI2C_ISR_TCR_Pos)
9054#define FMPI2C_ISR_TCR FMPI2C_ISR_TCR_Msk
9055#define FMPI2C_ISR_BERR_Pos (8U)
9056#define FMPI2C_ISR_BERR_Msk (0x1UL << FMPI2C_ISR_BERR_Pos)
9057#define FMPI2C_ISR_BERR FMPI2C_ISR_BERR_Msk
9058#define FMPI2C_ISR_ARLO_Pos (9U)
9059#define FMPI2C_ISR_ARLO_Msk (0x1UL << FMPI2C_ISR_ARLO_Pos)
9060#define FMPI2C_ISR_ARLO FMPI2C_ISR_ARLO_Msk
9061#define FMPI2C_ISR_OVR_Pos (10U)
9062#define FMPI2C_ISR_OVR_Msk (0x1UL << FMPI2C_ISR_OVR_Pos)
9063#define FMPI2C_ISR_OVR FMPI2C_ISR_OVR_Msk
9064#define FMPI2C_ISR_PECERR_Pos (11U)
9065#define FMPI2C_ISR_PECERR_Msk (0x1UL << FMPI2C_ISR_PECERR_Pos)
9066#define FMPI2C_ISR_PECERR FMPI2C_ISR_PECERR_Msk
9067#define FMPI2C_ISR_TIMEOUT_Pos (12U)
9068#define FMPI2C_ISR_TIMEOUT_Msk (0x1UL << FMPI2C_ISR_TIMEOUT_Pos)
9069#define FMPI2C_ISR_TIMEOUT FMPI2C_ISR_TIMEOUT_Msk
9070#define FMPI2C_ISR_ALERT_Pos (13U)
9071#define FMPI2C_ISR_ALERT_Msk (0x1UL << FMPI2C_ISR_ALERT_Pos)
9072#define FMPI2C_ISR_ALERT FMPI2C_ISR_ALERT_Msk
9073#define FMPI2C_ISR_BUSY_Pos (15U)
9074#define FMPI2C_ISR_BUSY_Msk (0x1UL << FMPI2C_ISR_BUSY_Pos)
9075#define FMPI2C_ISR_BUSY FMPI2C_ISR_BUSY_Msk
9076#define FMPI2C_ISR_DIR_Pos (16U)
9077#define FMPI2C_ISR_DIR_Msk (0x1UL << FMPI2C_ISR_DIR_Pos)
9078#define FMPI2C_ISR_DIR FMPI2C_ISR_DIR_Msk
9079#define FMPI2C_ISR_ADDCODE_Pos (17U)
9080#define FMPI2C_ISR_ADDCODE_Msk (0x7FUL << FMPI2C_ISR_ADDCODE_Pos)
9081#define FMPI2C_ISR_ADDCODE FMPI2C_ISR_ADDCODE_Msk
9082
9083/****************** Bit definition for I2C_ICR register *********************/
9084#define FMPI2C_ICR_ADDRCF_Pos (3U)
9085#define FMPI2C_ICR_ADDRCF_Msk (0x1UL << FMPI2C_ICR_ADDRCF_Pos)
9086#define FMPI2C_ICR_ADDRCF FMPI2C_ICR_ADDRCF_Msk
9087#define FMPI2C_ICR_NACKCF_Pos (4U)
9088#define FMPI2C_ICR_NACKCF_Msk (0x1UL << FMPI2C_ICR_NACKCF_Pos)
9089#define FMPI2C_ICR_NACKCF FMPI2C_ICR_NACKCF_Msk
9090#define FMPI2C_ICR_STOPCF_Pos (5U)
9091#define FMPI2C_ICR_STOPCF_Msk (0x1UL << FMPI2C_ICR_STOPCF_Pos)
9092#define FMPI2C_ICR_STOPCF FMPI2C_ICR_STOPCF_Msk
9093#define FMPI2C_ICR_BERRCF_Pos (8U)
9094#define FMPI2C_ICR_BERRCF_Msk (0x1UL << FMPI2C_ICR_BERRCF_Pos)
9095#define FMPI2C_ICR_BERRCF FMPI2C_ICR_BERRCF_Msk
9096#define FMPI2C_ICR_ARLOCF_Pos (9U)
9097#define FMPI2C_ICR_ARLOCF_Msk (0x1UL << FMPI2C_ICR_ARLOCF_Pos)
9098#define FMPI2C_ICR_ARLOCF FMPI2C_ICR_ARLOCF_Msk
9099#define FMPI2C_ICR_OVRCF_Pos (10U)
9100#define FMPI2C_ICR_OVRCF_Msk (0x1UL << FMPI2C_ICR_OVRCF_Pos)
9101#define FMPI2C_ICR_OVRCF FMPI2C_ICR_OVRCF_Msk
9102#define FMPI2C_ICR_PECCF_Pos (11U)
9103#define FMPI2C_ICR_PECCF_Msk (0x1UL << FMPI2C_ICR_PECCF_Pos)
9104#define FMPI2C_ICR_PECCF FMPI2C_ICR_PECCF_Msk
9105#define FMPI2C_ICR_TIMOUTCF_Pos (12U)
9106#define FMPI2C_ICR_TIMOUTCF_Msk (0x1UL << FMPI2C_ICR_TIMOUTCF_Pos)
9107#define FMPI2C_ICR_TIMOUTCF FMPI2C_ICR_TIMOUTCF_Msk
9108#define FMPI2C_ICR_ALERTCF_Pos (13U)
9109#define FMPI2C_ICR_ALERTCF_Msk (0x1UL << FMPI2C_ICR_ALERTCF_Pos)
9110#define FMPI2C_ICR_ALERTCF FMPI2C_ICR_ALERTCF_Msk
9111
9112/****************** Bit definition for I2C_PECR register *********************/
9113#define FMPI2C_PECR_PEC_Pos (0U)
9114#define FMPI2C_PECR_PEC_Msk (0xFFUL << FMPI2C_PECR_PEC_Pos)
9115#define FMPI2C_PECR_PEC FMPI2C_PECR_PEC_Msk
9116
9117/****************** Bit definition for I2C_RXDR register *********************/
9118#define FMPI2C_RXDR_RXDATA_Pos (0U)
9119#define FMPI2C_RXDR_RXDATA_Msk (0xFFUL << FMPI2C_RXDR_RXDATA_Pos)
9120#define FMPI2C_RXDR_RXDATA FMPI2C_RXDR_RXDATA_Msk
9121
9122/****************** Bit definition for I2C_TXDR register *********************/
9123#define FMPI2C_TXDR_TXDATA_Pos (0U)
9124#define FMPI2C_TXDR_TXDATA_Msk (0xFFUL << FMPI2C_TXDR_TXDATA_Pos)
9125#define FMPI2C_TXDR_TXDATA FMPI2C_TXDR_TXDATA_Msk
9126
9127
9128
9129/******************************************************************************/
9130/* */
9131/* Independent WATCHDOG */
9132/* */
9133/******************************************************************************/
9134/******************* Bit definition for IWDG_KR register ********************/
9135#define IWDG_KR_KEY_Pos (0U)
9136#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
9137#define IWDG_KR_KEY IWDG_KR_KEY_Msk
9138
9139/******************* Bit definition for IWDG_PR register ********************/
9140#define IWDG_PR_PR_Pos (0U)
9141#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
9142#define IWDG_PR_PR IWDG_PR_PR_Msk
9143#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
9144#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
9145#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
9146
9147/******************* Bit definition for IWDG_RLR register *******************/
9148#define IWDG_RLR_RL_Pos (0U)
9149#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
9150#define IWDG_RLR_RL IWDG_RLR_RL_Msk
9151
9152/******************* Bit definition for IWDG_SR register ********************/
9153#define IWDG_SR_PVU_Pos (0U)
9154#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
9155#define IWDG_SR_PVU IWDG_SR_PVU_Msk
9156#define IWDG_SR_RVU_Pos (1U)
9157#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
9158#define IWDG_SR_RVU IWDG_SR_RVU_Msk
9159
9160
9161
9162/******************************************************************************/
9163/* */
9164/* Power Control */
9165/* */
9166/******************************************************************************/
9167/******************** Bit definition for PWR_CR register ********************/
9168#define PWR_CR_LPDS_Pos (0U)
9169#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
9170#define PWR_CR_LPDS PWR_CR_LPDS_Msk
9171#define PWR_CR_PDDS_Pos (1U)
9172#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
9173#define PWR_CR_PDDS PWR_CR_PDDS_Msk
9174#define PWR_CR_CWUF_Pos (2U)
9175#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
9176#define PWR_CR_CWUF PWR_CR_CWUF_Msk
9177#define PWR_CR_CSBF_Pos (3U)
9178#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
9179#define PWR_CR_CSBF PWR_CR_CSBF_Msk
9180#define PWR_CR_PVDE_Pos (4U)
9181#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
9182#define PWR_CR_PVDE PWR_CR_PVDE_Msk
9183
9184#define PWR_CR_PLS_Pos (5U)
9185#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
9186#define PWR_CR_PLS PWR_CR_PLS_Msk
9187#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
9188#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
9189#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
9190
9192#define PWR_CR_PLS_LEV0 0x00000000U
9193#define PWR_CR_PLS_LEV1 0x00000020U
9194#define PWR_CR_PLS_LEV2 0x00000040U
9195#define PWR_CR_PLS_LEV3 0x00000060U
9196#define PWR_CR_PLS_LEV4 0x00000080U
9197#define PWR_CR_PLS_LEV5 0x000000A0U
9198#define PWR_CR_PLS_LEV6 0x000000C0U
9199#define PWR_CR_PLS_LEV7 0x000000E0U
9200#define PWR_CR_DBP_Pos (8U)
9201#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
9202#define PWR_CR_DBP PWR_CR_DBP_Msk
9203#define PWR_CR_FPDS_Pos (9U)
9204#define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)
9205#define PWR_CR_FPDS PWR_CR_FPDS_Msk
9206#define PWR_CR_LPLVDS_Pos (10U)
9207#define PWR_CR_LPLVDS_Msk (0x1UL << PWR_CR_LPLVDS_Pos)
9208#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk
9209#define PWR_CR_MRLVDS_Pos (11U)
9210#define PWR_CR_MRLVDS_Msk (0x1UL << PWR_CR_MRLVDS_Pos)
9211#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk
9212#define PWR_CR_ADCDC1_Pos (13U)
9213#define PWR_CR_ADCDC1_Msk (0x1UL << PWR_CR_ADCDC1_Pos)
9214#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk
9215#define PWR_CR_VOS_Pos (14U)
9216#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos)
9217#define PWR_CR_VOS PWR_CR_VOS_Msk
9218#define PWR_CR_VOS_0 0x00004000U
9219#define PWR_CR_VOS_1 0x00008000U
9220#define PWR_CR_FMSSR_Pos (20U)
9221#define PWR_CR_FMSSR_Msk (0x1UL << PWR_CR_FMSSR_Pos)
9222#define PWR_CR_FMSSR PWR_CR_FMSSR_Msk
9223#define PWR_CR_FISSR_Pos (21U)
9224#define PWR_CR_FISSR_Msk (0x1UL << PWR_CR_FISSR_Pos)
9225#define PWR_CR_FISSR PWR_CR_FISSR_Msk
9226
9227
9228/******************* Bit definition for PWR_CSR register ********************/
9229#define PWR_CSR_WUF_Pos (0U)
9230#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
9231#define PWR_CSR_WUF PWR_CSR_WUF_Msk
9232#define PWR_CSR_SBF_Pos (1U)
9233#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
9234#define PWR_CSR_SBF PWR_CSR_SBF_Msk
9235#define PWR_CSR_PVDO_Pos (2U)
9236#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
9237#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
9238#define PWR_CSR_BRR_Pos (3U)
9239#define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)
9240#define PWR_CSR_BRR PWR_CSR_BRR_Msk
9241#define PWR_CSR_EWUP3_Pos (6U)
9242#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos)
9243#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk
9244#define PWR_CSR_EWUP2_Pos (7U)
9245#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos)
9246#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk
9247#define PWR_CSR_EWUP1_Pos (8U)
9248#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos)
9249#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk
9250#define PWR_CSR_BRE_Pos (9U)
9251#define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)
9252#define PWR_CSR_BRE PWR_CSR_BRE_Msk
9253#define PWR_CSR_VOSRDY_Pos (14U)
9254#define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos)
9255#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk
9256
9257
9258/******************************************************************************/
9259/* */
9260/* QUADSPI */
9261/* */
9262/******************************************************************************/
9263/***************** Bit definition for QUADSPI_CR register *******************/
9264#define QUADSPI_CR_EN_Pos (0U)
9265#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
9266#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
9267#define QUADSPI_CR_ABORT_Pos (1U)
9268#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
9269#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
9270#define QUADSPI_CR_DMAEN_Pos (2U)
9271#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
9272#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
9273#define QUADSPI_CR_TCEN_Pos (3U)
9274#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
9275#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
9276#define QUADSPI_CR_SSHIFT_Pos (4U)
9277#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
9278#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
9279#define QUADSPI_CR_DFM_Pos (6U)
9280#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
9281#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
9282#define QUADSPI_CR_FSEL_Pos (7U)
9283#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
9284#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
9285#define QUADSPI_CR_FTHRES_Pos (8U)
9286#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos)
9287#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
9288#define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos)
9289#define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos)
9290#define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos)
9291#define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos)
9292#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos)
9293#define QUADSPI_CR_TEIE_Pos (16U)
9294#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
9295#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
9296#define QUADSPI_CR_TCIE_Pos (17U)
9297#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
9298#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
9299#define QUADSPI_CR_FTIE_Pos (18U)
9300#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
9301#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
9302#define QUADSPI_CR_SMIE_Pos (19U)
9303#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
9304#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
9305#define QUADSPI_CR_TOIE_Pos (20U)
9306#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
9307#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
9308#define QUADSPI_CR_APMS_Pos (22U)
9309#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
9310#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
9311#define QUADSPI_CR_PMM_Pos (23U)
9312#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
9313#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
9314#define QUADSPI_CR_PRESCALER_Pos (24U)
9315#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
9316#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
9317#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos)
9318#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos)
9319#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos)
9320#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos)
9321#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos)
9322#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos)
9323#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos)
9324#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos)
9325
9326/***************** Bit definition for QUADSPI_DCR register ******************/
9327#define QUADSPI_DCR_CKMODE_Pos (0U)
9328#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
9329#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
9330#define QUADSPI_DCR_CSHT_Pos (8U)
9331#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
9332#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
9333#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
9334#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
9335#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
9336#define QUADSPI_DCR_FSIZE_Pos (16U)
9337#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
9338#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
9339#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos)
9340#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos)
9341#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos)
9342#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos)
9343#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos)
9344
9345/****************** Bit definition for QUADSPI_SR register *******************/
9346#define QUADSPI_SR_TEF_Pos (0U)
9347#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
9348#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
9349#define QUADSPI_SR_TCF_Pos (1U)
9350#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
9351#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
9352#define QUADSPI_SR_FTF_Pos (2U)
9353#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
9354#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
9355#define QUADSPI_SR_SMF_Pos (3U)
9356#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
9357#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
9358#define QUADSPI_SR_TOF_Pos (4U)
9359#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
9360#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
9361#define QUADSPI_SR_BUSY_Pos (5U)
9362#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
9363#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
9364#define QUADSPI_SR_FLEVEL_Pos (8U)
9365#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos)
9366#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
9367#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos)
9368#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos)
9369#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos)
9370#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos)
9371#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos)
9372#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos)
9373
9374/****************** Bit definition for QUADSPI_FCR register ******************/
9375#define QUADSPI_FCR_CTEF_Pos (0U)
9376#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
9377#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
9378#define QUADSPI_FCR_CTCF_Pos (1U)
9379#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
9380#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
9381#define QUADSPI_FCR_CSMF_Pos (3U)
9382#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
9383#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
9384#define QUADSPI_FCR_CTOF_Pos (4U)
9385#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
9386#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
9387
9388/****************** Bit definition for QUADSPI_DLR register ******************/
9389#define QUADSPI_DLR_DL_Pos (0U)
9390#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
9391#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
9392
9393/****************** Bit definition for QUADSPI_CCR register ******************/
9394#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
9395#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
9396#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
9397#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos)
9398#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos)
9399#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos)
9400#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos)
9401#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos)
9402#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos)
9403#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos)
9404#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos)
9405#define QUADSPI_CCR_IMODE_Pos (8U)
9406#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
9407#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
9408#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
9409#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
9410#define QUADSPI_CCR_ADMODE_Pos (10U)
9411#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
9412#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
9413#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
9414#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
9415#define QUADSPI_CCR_ADSIZE_Pos (12U)
9416#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
9417#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
9418#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
9419#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
9420#define QUADSPI_CCR_ABMODE_Pos (14U)
9421#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
9422#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
9423#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
9424#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
9425#define QUADSPI_CCR_ABSIZE_Pos (16U)
9426#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
9427#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
9428#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
9429#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
9430#define QUADSPI_CCR_DCYC_Pos (18U)
9431#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
9432#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
9433#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos)
9434#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos)
9435#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos)
9436#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos)
9437#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos)
9438#define QUADSPI_CCR_DMODE_Pos (24U)
9439#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
9440#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
9441#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
9442#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
9443#define QUADSPI_CCR_FMODE_Pos (26U)
9444#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
9445#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
9446#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
9447#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
9448#define QUADSPI_CCR_SIOO_Pos (28U)
9449#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
9450#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
9451#define QUADSPI_CCR_DHHC_Pos (30U)
9452#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
9453#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
9454#define QUADSPI_CCR_DDRM_Pos (31U)
9455#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
9456#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
9457/****************** Bit definition for QUADSPI_AR register *******************/
9458#define QUADSPI_AR_ADDRESS_Pos (0U)
9459#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
9460#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
9461
9462/****************** Bit definition for QUADSPI_ABR register ******************/
9463#define QUADSPI_ABR_ALTERNATE_Pos (0U)
9464#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
9465#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
9466
9467/****************** Bit definition for QUADSPI_DR register *******************/
9468#define QUADSPI_DR_DATA_Pos (0U)
9469#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
9470#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
9471
9472/****************** Bit definition for QUADSPI_PSMKR register ****************/
9473#define QUADSPI_PSMKR_MASK_Pos (0U)
9474#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
9475#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
9476
9477/****************** Bit definition for QUADSPI_PSMAR register ****************/
9478#define QUADSPI_PSMAR_MATCH_Pos (0U)
9479#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
9480#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
9481
9482/****************** Bit definition for QUADSPI_PIR register *****************/
9483#define QUADSPI_PIR_INTERVAL_Pos (0U)
9484#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
9485#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
9486
9487/****************** Bit definition for QUADSPI_LPTR register *****************/
9488#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
9489#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
9490#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
9491
9492/******************************************************************************/
9493/* */
9494/* Reset and Clock Control */
9495/* */
9496/******************************************************************************/
9497/******************** Bit definition for RCC_CR register ********************/
9498#define RCC_CR_HSION_Pos (0U)
9499#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
9500#define RCC_CR_HSION RCC_CR_HSION_Msk
9501#define RCC_CR_HSIRDY_Pos (1U)
9502#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
9503#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
9504
9505#define RCC_CR_HSITRIM_Pos (3U)
9506#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
9507#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
9508#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
9509#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
9510#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
9511#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
9512#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
9513
9514#define RCC_CR_HSICAL_Pos (8U)
9515#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
9516#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
9517#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
9518#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
9519#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
9520#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
9521#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
9522#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
9523#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
9524#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
9525
9526#define RCC_CR_HSEON_Pos (16U)
9527#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
9528#define RCC_CR_HSEON RCC_CR_HSEON_Msk
9529#define RCC_CR_HSERDY_Pos (17U)
9530#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
9531#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
9532#define RCC_CR_HSEBYP_Pos (18U)
9533#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
9534#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
9535#define RCC_CR_CSSON_Pos (19U)
9536#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
9537#define RCC_CR_CSSON RCC_CR_CSSON_Msk
9538#define RCC_CR_PLLON_Pos (24U)
9539#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
9540#define RCC_CR_PLLON RCC_CR_PLLON_Msk
9541#define RCC_CR_PLLRDY_Pos (25U)
9542#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
9543#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
9544/*
9545 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
9546 */
9547#define RCC_PLLI2S_SUPPORT
9548
9549#define RCC_CR_PLLI2SON_Pos (26U)
9550#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
9551#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
9552#define RCC_CR_PLLI2SRDY_Pos (27U)
9553#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
9554#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
9555
9556/******************** Bit definition for RCC_PLLCFGR register ***************/
9557#define RCC_PLLCFGR_PLLM_Pos (0U)
9558#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
9559#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
9560#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
9561#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
9562#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
9563#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
9564#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
9565#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
9566
9567#define RCC_PLLCFGR_PLLN_Pos (6U)
9568#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
9569#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
9570#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
9571#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
9572#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
9573#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
9574#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
9575#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
9576#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
9577#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
9578#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
9579
9580#define RCC_PLLCFGR_PLLP_Pos (16U)
9581#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
9582#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
9583#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
9584#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
9585
9586#define RCC_PLLCFGR_PLLSRC_Pos (22U)
9587#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
9588#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
9589#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
9590#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
9591#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
9592#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
9593
9594#define RCC_PLLCFGR_PLLQ_Pos (24U)
9595#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
9596#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
9597#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
9598#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
9599#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
9600#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
9601/*
9602 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
9603 */
9604#define RCC_PLLR_I2S_CLKSOURCE_SUPPORT
9605
9606#define RCC_PLLCFGR_PLLR_Pos (28U)
9607#define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos)
9608#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
9609#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)
9610#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)
9611#define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos)
9612
9613/******************** Bit definition for RCC_CFGR register ******************/
9615#define RCC_CFGR_SW_Pos (0U)
9616#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
9617#define RCC_CFGR_SW RCC_CFGR_SW_Msk
9618#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
9619#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
9620
9621#define RCC_CFGR_SW_HSI 0x00000000U
9622#define RCC_CFGR_SW_HSE 0x00000001U
9623#define RCC_CFGR_SW_PLL 0x00000002U
9624
9626#define RCC_CFGR_SWS_Pos (2U)
9627#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
9628#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
9629#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
9630#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
9631
9632#define RCC_CFGR_SWS_HSI 0x00000000U
9633#define RCC_CFGR_SWS_HSE 0x00000004U
9634#define RCC_CFGR_SWS_PLL 0x00000008U
9635
9637#define RCC_CFGR_HPRE_Pos (4U)
9638#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
9639#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
9640#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
9641#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
9642#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
9643#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
9644
9645#define RCC_CFGR_HPRE_DIV1 0x00000000U
9646#define RCC_CFGR_HPRE_DIV2 0x00000080U
9647#define RCC_CFGR_HPRE_DIV4 0x00000090U
9648#define RCC_CFGR_HPRE_DIV8 0x000000A0U
9649#define RCC_CFGR_HPRE_DIV16 0x000000B0U
9650#define RCC_CFGR_HPRE_DIV64 0x000000C0U
9651#define RCC_CFGR_HPRE_DIV128 0x000000D0U
9652#define RCC_CFGR_HPRE_DIV256 0x000000E0U
9653#define RCC_CFGR_HPRE_DIV512 0x000000F0U
9654
9656#define RCC_CFGR_PPRE1_Pos (10U)
9657#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
9658#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
9659#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
9660#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
9661#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
9662
9663#define RCC_CFGR_PPRE1_DIV1 0x00000000U
9664#define RCC_CFGR_PPRE1_DIV2 0x00001000U
9665#define RCC_CFGR_PPRE1_DIV4 0x00001400U
9666#define RCC_CFGR_PPRE1_DIV8 0x00001800U
9667#define RCC_CFGR_PPRE1_DIV16 0x00001C00U
9668
9670#define RCC_CFGR_PPRE2_Pos (13U)
9671#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
9672#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
9673#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
9674#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
9675#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
9676
9677#define RCC_CFGR_PPRE2_DIV1 0x00000000U
9678#define RCC_CFGR_PPRE2_DIV2 0x00008000U
9679#define RCC_CFGR_PPRE2_DIV4 0x0000A000U
9680#define RCC_CFGR_PPRE2_DIV8 0x0000C000U
9681#define RCC_CFGR_PPRE2_DIV16 0x0000E000U
9682
9684#define RCC_CFGR_RTCPRE_Pos (16U)
9685#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
9686#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
9687#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
9688#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
9689#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
9690#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
9691#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
9692
9694#define RCC_CFGR_MCO1_Pos (21U)
9695#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
9696#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
9697#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
9698#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
9699
9700
9701#define RCC_CFGR_MCO1PRE_Pos (24U)
9702#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
9703#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
9704#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
9705#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
9706#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
9707
9708#define RCC_CFGR_MCO2PRE_Pos (27U)
9709#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
9710#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
9711#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
9712#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
9713#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
9714
9715#define RCC_CFGR_MCO2_Pos (30U)
9716#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
9717#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
9718#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
9719#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
9720
9721/******************** Bit definition for RCC_CIR register *******************/
9722#define RCC_CIR_LSIRDYF_Pos (0U)
9723#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
9724#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
9725#define RCC_CIR_LSERDYF_Pos (1U)
9726#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
9727#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
9728#define RCC_CIR_HSIRDYF_Pos (2U)
9729#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
9730#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
9731#define RCC_CIR_HSERDYF_Pos (3U)
9732#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
9733#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
9734#define RCC_CIR_PLLRDYF_Pos (4U)
9735#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
9736#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
9737#define RCC_CIR_PLLI2SRDYF_Pos (5U)
9738#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
9739#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
9740
9741#define RCC_CIR_CSSF_Pos (7U)
9742#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
9743#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
9744#define RCC_CIR_LSIRDYIE_Pos (8U)
9745#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
9746#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
9747#define RCC_CIR_LSERDYIE_Pos (9U)
9748#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
9749#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
9750#define RCC_CIR_HSIRDYIE_Pos (10U)
9751#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
9752#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
9753#define RCC_CIR_HSERDYIE_Pos (11U)
9754#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
9755#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
9756#define RCC_CIR_PLLRDYIE_Pos (12U)
9757#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
9758#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
9759#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
9760#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
9761#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
9762
9763#define RCC_CIR_LSIRDYC_Pos (16U)
9764#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
9765#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
9766#define RCC_CIR_LSERDYC_Pos (17U)
9767#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
9768#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
9769#define RCC_CIR_HSIRDYC_Pos (18U)
9770#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
9771#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
9772#define RCC_CIR_HSERDYC_Pos (19U)
9773#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
9774#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
9775#define RCC_CIR_PLLRDYC_Pos (20U)
9776#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
9777#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
9778#define RCC_CIR_PLLI2SRDYC_Pos (21U)
9779#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
9780#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
9781
9782#define RCC_CIR_CSSC_Pos (23U)
9783#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
9784#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
9785
9786/******************** Bit definition for RCC_AHB1RSTR register **************/
9787#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
9788#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
9789#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
9790#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
9791#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
9792#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
9793#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
9794#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
9795#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
9796#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
9797#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
9798#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
9799#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
9800#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
9801#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
9802#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
9803#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
9804#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
9805#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
9806#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
9807#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
9808#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
9809#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
9810#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
9811#define RCC_AHB1RSTR_CRCRST_Pos (12U)
9812#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
9813#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
9814#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
9815#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
9816#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
9817#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
9818#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
9819#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
9820
9821/******************** Bit definition for RCC_AHB2RSTR register **************/
9822#define RCC_AHB2RSTR_AESRST_Pos (4U)
9823#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos)
9824#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk
9825#define RCC_AHB2RSTR_RNGRST_Pos (6U)
9826#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
9827#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
9828#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
9829#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
9830#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
9831/******************** Bit definition for RCC_AHB3RSTR register **************/
9832#define RCC_AHB3RSTR_FSMCRST_Pos (0U)
9833#define RCC_AHB3RSTR_FSMCRST_Msk (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)
9834#define RCC_AHB3RSTR_FSMCRST RCC_AHB3RSTR_FSMCRST_Msk
9835#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
9836#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
9837#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
9838
9839
9840/******************** Bit definition for RCC_APB1RSTR register **************/
9841#define RCC_APB1RSTR_TIM2RST_Pos (0U)
9842#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
9843#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
9844#define RCC_APB1RSTR_TIM3RST_Pos (1U)
9845#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
9846#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
9847#define RCC_APB1RSTR_TIM4RST_Pos (2U)
9848#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
9849#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
9850#define RCC_APB1RSTR_TIM5RST_Pos (3U)
9851#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
9852#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
9853#define RCC_APB1RSTR_TIM6RST_Pos (4U)
9854#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
9855#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
9856#define RCC_APB1RSTR_TIM7RST_Pos (5U)
9857#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
9858#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
9859#define RCC_APB1RSTR_TIM12RST_Pos (6U)
9860#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
9861#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
9862#define RCC_APB1RSTR_TIM13RST_Pos (7U)
9863#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
9864#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
9865#define RCC_APB1RSTR_TIM14RST_Pos (8U)
9866#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
9867#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
9868#define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
9869#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)
9870#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
9871#define RCC_APB1RSTR_WWDGRST_Pos (11U)
9872#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
9873#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
9874#define RCC_APB1RSTR_SPI2RST_Pos (14U)
9875#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
9876#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
9877#define RCC_APB1RSTR_SPI3RST_Pos (15U)
9878#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
9879#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
9880#define RCC_APB1RSTR_USART2RST_Pos (17U)
9881#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
9882#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
9883#define RCC_APB1RSTR_USART3RST_Pos (18U)
9884#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
9885#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
9886#define RCC_APB1RSTR_UART4RST_Pos (19U)
9887#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
9888#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
9889#define RCC_APB1RSTR_UART5RST_Pos (20U)
9890#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
9891#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
9892#define RCC_APB1RSTR_I2C1RST_Pos (21U)
9893#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
9894#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
9895#define RCC_APB1RSTR_I2C2RST_Pos (22U)
9896#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
9897#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
9898#define RCC_APB1RSTR_I2C3RST_Pos (23U)
9899#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
9900#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
9901#define RCC_APB1RSTR_FMPI2C1RST_Pos (24U)
9902#define RCC_APB1RSTR_FMPI2C1RST_Msk (0x1UL << RCC_APB1RSTR_FMPI2C1RST_Pos)
9903#define RCC_APB1RSTR_FMPI2C1RST RCC_APB1RSTR_FMPI2C1RST_Msk
9904#define RCC_APB1RSTR_CAN1RST_Pos (25U)
9905#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
9906#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
9907#define RCC_APB1RSTR_CAN2RST_Pos (26U)
9908#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
9909#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
9910#define RCC_APB1RSTR_CAN3RST_Pos (27U)
9911#define RCC_APB1RSTR_CAN3RST_Msk (0x1UL << RCC_APB1RSTR_CAN3RST_Pos)
9912#define RCC_APB1RSTR_CAN3RST RCC_APB1RSTR_CAN3RST_Msk
9913#define RCC_APB1RSTR_PWRRST_Pos (28U)
9914#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
9915#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
9916#define RCC_APB1RSTR_DACRST_Pos (29U)
9917#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
9918#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
9919#define RCC_APB1RSTR_UART7RST_Pos (30U)
9920#define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos)
9921#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
9922#define RCC_APB1RSTR_UART8RST_Pos (31U)
9923#define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos)
9924#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
9925
9926/******************** Bit definition for RCC_APB2RSTR register **************/
9927#define RCC_APB2RSTR_TIM1RST_Pos (0U)
9928#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
9929#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
9930#define RCC_APB2RSTR_TIM8RST_Pos (1U)
9931#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
9932#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
9933#define RCC_APB2RSTR_USART1RST_Pos (4U)
9934#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
9935#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
9936#define RCC_APB2RSTR_USART6RST_Pos (5U)
9937#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
9938#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
9939#define RCC_APB2RSTR_UART9RST_Pos (6U)
9940#define RCC_APB2RSTR_UART9RST_Msk (0x1UL << RCC_APB2RSTR_UART9RST_Pos)
9941#define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk
9942#define RCC_APB2RSTR_UART10RST_Pos (7U)
9943#define RCC_APB2RSTR_UART10RST_Msk (0x1UL << RCC_APB2RSTR_UART10RST_Pos)
9944#define RCC_APB2RSTR_UART10RST RCC_APB2RSTR_UART10RST_Msk
9945#define RCC_APB2RSTR_ADCRST_Pos (8U)
9946#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
9947#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
9948#define RCC_APB2RSTR_SDIORST_Pos (11U)
9949#define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
9950#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
9951#define RCC_APB2RSTR_SPI1RST_Pos (12U)
9952#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
9953#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
9954#define RCC_APB2RSTR_SPI4RST_Pos (13U)
9955#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
9956#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
9957#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
9958#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
9959#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
9960#define RCC_APB2RSTR_TIM9RST_Pos (16U)
9961#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
9962#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
9963#define RCC_APB2RSTR_TIM10RST_Pos (17U)
9964#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
9965#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
9966#define RCC_APB2RSTR_TIM11RST_Pos (18U)
9967#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
9968#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
9969#define RCC_APB2RSTR_SPI5RST_Pos (20U)
9970#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
9971#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
9972#define RCC_APB2RSTR_SAI1RST_Pos (22U)
9973#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
9974#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
9975#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
9976#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos)
9977#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
9978#define RCC_APB2RSTR_DFSDM2RST_Pos (25U)
9979#define RCC_APB2RSTR_DFSDM2RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM2RST_Pos)
9980#define RCC_APB2RSTR_DFSDM2RST RCC_APB2RSTR_DFSDM2RST_Msk
9981
9982/******************** Bit definition for RCC_AHB1ENR register ***************/
9983#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
9984#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
9985#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
9986#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
9987#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
9988#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
9989#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
9990#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
9991#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
9992#define RCC_AHB1ENR_GPIODEN_Pos (3U)
9993#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
9994#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
9995#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
9996#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
9997#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
9998#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
9999#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
10000#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
10001#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
10002#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
10003#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
10004#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
10005#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
10006#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
10007#define RCC_AHB1ENR_CRCEN_Pos (12U)
10008#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
10009#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
10010#define RCC_AHB1ENR_DMA1EN_Pos (21U)
10011#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
10012#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
10013#define RCC_AHB1ENR_DMA2EN_Pos (22U)
10014#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
10015#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
10016/******************** Bit definition for RCC_AHB2ENR register ***************/
10017/*
10018 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
10019 */
10020#define RCC_AHB2_SUPPORT
10021
10022#define RCC_AHB2ENR_AESEN_Pos (4U)
10023#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos)
10024#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk
10025#define RCC_AHB2ENR_RNGEN_Pos (6U)
10026#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
10027#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
10028#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
10029#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
10030#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
10031
10032/******************** Bit definition for RCC_AHB3ENR register ***************/
10033/*
10034 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
10035 */
10036#define RCC_AHB3_SUPPORT
10037
10038#define RCC_AHB3ENR_FSMCEN_Pos (0U)
10039#define RCC_AHB3ENR_FSMCEN_Msk (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)
10040#define RCC_AHB3ENR_FSMCEN RCC_AHB3ENR_FSMCEN_Msk
10041#define RCC_AHB3ENR_QSPIEN_Pos (1U)
10042#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
10043#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
10044
10045/******************** Bit definition for RCC_APB1ENR register ***************/
10046#define RCC_APB1ENR_TIM2EN_Pos (0U)
10047#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
10048#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
10049#define RCC_APB1ENR_TIM3EN_Pos (1U)
10050#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
10051#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
10052#define RCC_APB1ENR_TIM4EN_Pos (2U)
10053#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
10054#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
10055#define RCC_APB1ENR_TIM5EN_Pos (3U)
10056#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
10057#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
10058#define RCC_APB1ENR_TIM6EN_Pos (4U)
10059#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
10060#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
10061#define RCC_APB1ENR_TIM7EN_Pos (5U)
10062#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
10063#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
10064#define RCC_APB1ENR_TIM12EN_Pos (6U)
10065#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
10066#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
10067#define RCC_APB1ENR_TIM13EN_Pos (7U)
10068#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
10069#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
10070#define RCC_APB1ENR_TIM14EN_Pos (8U)
10071#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
10072#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
10073#define RCC_APB1ENR_LPTIM1EN_Pos (9U)
10074#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)
10075#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
10076#define RCC_APB1ENR_RTCAPBEN_Pos (10U)
10077#define RCC_APB1ENR_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR_RTCAPBEN_Pos)
10078#define RCC_APB1ENR_RTCAPBEN RCC_APB1ENR_RTCAPBEN_Msk
10079#define RCC_APB1ENR_WWDGEN_Pos (11U)
10080#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
10081#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
10082#define RCC_APB1ENR_SPI2EN_Pos (14U)
10083#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
10084#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
10085#define RCC_APB1ENR_SPI3EN_Pos (15U)
10086#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
10087#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
10088#define RCC_APB1ENR_USART2EN_Pos (17U)
10089#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
10090#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
10091#define RCC_APB1ENR_USART3EN_Pos (18U)
10092#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
10093#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
10094#define RCC_APB1ENR_UART4EN_Pos (19U)
10095#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
10096#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
10097#define RCC_APB1ENR_UART5EN_Pos (20U)
10098#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
10099#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
10100#define RCC_APB1ENR_I2C1EN_Pos (21U)
10101#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
10102#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
10103#define RCC_APB1ENR_I2C2EN_Pos (22U)
10104#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
10105#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
10106#define RCC_APB1ENR_I2C3EN_Pos (23U)
10107#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
10108#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
10109#define RCC_APB1ENR_FMPI2C1EN_Pos (24U)
10110#define RCC_APB1ENR_FMPI2C1EN_Msk (0x1UL << RCC_APB1ENR_FMPI2C1EN_Pos)
10111#define RCC_APB1ENR_FMPI2C1EN RCC_APB1ENR_FMPI2C1EN_Msk
10112#define RCC_APB1ENR_CAN1EN_Pos (25U)
10113#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
10114#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
10115#define RCC_APB1ENR_CAN2EN_Pos (26U)
10116#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
10117#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
10118#define RCC_APB1ENR_CAN3EN_Pos (27U)
10119#define RCC_APB1ENR_CAN3EN_Msk (0x1UL << RCC_APB1ENR_CAN3EN_Pos)
10120#define RCC_APB1ENR_CAN3EN RCC_APB1ENR_CAN3EN_Msk
10121#define RCC_APB1ENR_PWREN_Pos (28U)
10122#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
10123#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
10124#define RCC_APB1ENR_DACEN_Pos (29U)
10125#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
10126#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
10127#define RCC_APB1ENR_UART7EN_Pos (30U)
10128#define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos)
10129#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
10130#define RCC_APB1ENR_UART8EN_Pos (31U)
10131#define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos)
10132#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
10133
10134/******************** Bit definition for RCC_APB2ENR register ***************/
10135#define RCC_APB2ENR_TIM1EN_Pos (0U)
10136#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
10137#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
10138#define RCC_APB2ENR_TIM8EN_Pos (1U)
10139#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
10140#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
10141#define RCC_APB2ENR_USART1EN_Pos (4U)
10142#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
10143#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
10144#define RCC_APB2ENR_USART6EN_Pos (5U)
10145#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
10146#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
10147#define RCC_APB2ENR_UART9EN_Pos (6U)
10148#define RCC_APB2ENR_UART9EN_Msk (0x1UL << RCC_APB2ENR_UART9EN_Pos)
10149#define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk
10150#define RCC_APB2ENR_UART10EN_Pos (7U)
10151#define RCC_APB2ENR_UART10EN_Msk (0x1UL << RCC_APB2ENR_UART10EN_Pos)
10152#define RCC_APB2ENR_UART10EN RCC_APB2ENR_UART10EN_Msk
10153#define RCC_APB2ENR_ADC1EN_Pos (8U)
10154#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
10155#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
10156#define RCC_APB2ENR_SDIOEN_Pos (11U)
10157#define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
10158#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
10159#define RCC_APB2ENR_SPI1EN_Pos (12U)
10160#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
10161#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
10162#define RCC_APB2ENR_SPI4EN_Pos (13U)
10163#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
10164#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
10165#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
10166#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
10167#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
10168#define RCC_APB2ENR_EXTITEN_Pos (15U)
10169#define RCC_APB2ENR_EXTITEN_Msk (0x1UL << RCC_APB2ENR_EXTITEN_Pos)
10170#define RCC_APB2ENR_EXTITEN RCC_APB2ENR_EXTITEN_Msk
10171#define RCC_APB2ENR_TIM9EN_Pos (16U)
10172#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
10173#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
10174#define RCC_APB2ENR_TIM10EN_Pos (17U)
10175#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
10176#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
10177#define RCC_APB2ENR_TIM11EN_Pos (18U)
10178#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
10179#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
10180#define RCC_APB2ENR_SPI5EN_Pos (20U)
10181#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
10182#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
10183#define RCC_APB2ENR_SAI1EN_Pos (22U)
10184#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
10185#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
10186#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
10187#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)
10188#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
10189#define RCC_APB2ENR_DFSDM2EN_Pos (25U)
10190#define RCC_APB2ENR_DFSDM2EN_Msk (0x1UL << RCC_APB2ENR_DFSDM2EN_Pos)
10191#define RCC_APB2ENR_DFSDM2EN RCC_APB2ENR_DFSDM2EN_Msk
10192
10193/******************** Bit definition for RCC_AHB1LPENR register *************/
10194#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
10195#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
10196#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
10197#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
10198#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
10199#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
10200#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
10201#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
10202#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
10203#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
10204#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
10205#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
10206#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
10207#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
10208#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
10209#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
10210#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
10211#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
10212#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
10213#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
10214#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
10215#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
10216#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
10217#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
10218#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
10219#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
10220#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
10221#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
10222#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
10223#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
10224#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
10225#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
10226#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
10227#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
10228#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
10229#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
10230#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
10231#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
10232#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
10233#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
10234#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
10235#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
10236
10237
10238/******************** Bit definition for RCC_AHB2LPENR register *************/
10239#define RCC_AHB2LPENR_AESLPEN_Pos (4U)
10240#define RCC_AHB2LPENR_AESLPEN_Msk (0x1UL << RCC_AHB2LPENR_AESLPEN_Pos)
10241#define RCC_AHB2LPENR_AESLPEN RCC_AHB2LPENR_AESLPEN_Msk
10242#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
10243#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
10244#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
10245#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
10246#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
10247#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
10248
10249/******************** Bit definition for RCC_AHB3LPENR register *************/
10250#define RCC_AHB3LPENR_FSMCLPEN_Pos (0U)
10251#define RCC_AHB3LPENR_FSMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos)
10252#define RCC_AHB3LPENR_FSMCLPEN RCC_AHB3LPENR_FSMCLPEN_Msk
10253#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
10254#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)
10255#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
10256
10257/******************** Bit definition for RCC_APB1LPENR register *************/
10258#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
10259#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
10260#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
10261#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
10262#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
10263#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
10264#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
10265#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
10266#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
10267#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
10268#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
10269#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
10270#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
10271#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
10272#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
10273#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
10274#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
10275#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
10276#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
10277#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
10278#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
10279#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
10280#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
10281#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
10282#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
10283#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
10284#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
10285#define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
10286#define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos)
10287#define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
10288#define RCC_APB1LPENR_RTCAPBLPEN_Pos (10U)
10289#define RCC_APB1LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB1LPENR_RTCAPBLPEN_Pos)
10290#define RCC_APB1LPENR_RTCAPBLPEN RCC_APB1LPENR_RTCAPBLPEN_Msk
10291#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
10292#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
10293#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
10294#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
10295#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
10296#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
10297#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
10298#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
10299#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
10300#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
10301#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
10302#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
10303#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
10304#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
10305#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
10306#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
10307#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
10308#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
10309#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
10310#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
10311#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
10312#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
10313#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
10314#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
10315#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
10316#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
10317#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
10318#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
10319#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
10320#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
10321#define RCC_APB1LPENR_FMPI2C1LPEN_Pos (24U)
10322#define RCC_APB1LPENR_FMPI2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_FMPI2C1LPEN_Pos)
10323#define RCC_APB1LPENR_FMPI2C1LPEN RCC_APB1LPENR_FMPI2C1LPEN_Msk
10324#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
10325#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
10326#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
10327#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
10328#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
10329#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
10330#define RCC_APB1LPENR_CAN3LPEN_Pos (27U)
10331#define RCC_APB1LPENR_CAN3LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN3LPEN_Pos)
10332#define RCC_APB1LPENR_CAN3LPEN RCC_APB1LPENR_CAN3LPEN_Msk
10333#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
10334#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
10335#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
10336#define RCC_APB1LPENR_DACLPEN_Pos (29U)
10337#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
10338#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
10339#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
10340#define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos)
10341#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
10342#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
10343#define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos)
10344#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
10345
10346/******************** Bit definition for RCC_APB2LPENR register *************/
10347#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
10348#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
10349#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
10350#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
10351#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
10352#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
10353#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
10354#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
10355#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
10356#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
10357#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
10358#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
10359#define RCC_APB2LPENR_UART9LPEN_Pos (6U)
10360#define RCC_APB2LPENR_UART9LPEN_Msk (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)
10361#define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk
10362#define RCC_APB2LPENR_UART10LPEN_Pos (7U)
10363#define RCC_APB2LPENR_UART10LPEN_Msk (0x1UL << RCC_APB2LPENR_UART10LPEN_Pos)
10364#define RCC_APB2LPENR_UART10LPEN RCC_APB2LPENR_UART10LPEN_Msk
10365#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
10366#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
10367#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
10368#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
10369#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
10370#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
10371#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
10372#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
10373#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
10374#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
10375#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
10376#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
10377#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
10378#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
10379#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
10380#define RCC_APB2LPENR_EXTITLPEN_Pos (15U)
10381#define RCC_APB2LPENR_EXTITLPEN_Msk (0x1UL << RCC_APB2LPENR_EXTITLPEN_Pos)
10382#define RCC_APB2LPENR_EXTITLPEN RCC_APB2LPENR_EXTITLPEN_Msk
10383#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
10384#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
10385#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
10386#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
10387#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
10388#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
10389#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
10390#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
10391#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
10392#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
10393#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
10394#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
10395#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
10396#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
10397#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
10398#define RCC_APB2LPENR_DFSDM1LPEN_Pos (24U)
10399#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos)
10400#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
10401#define RCC_APB2LPENR_DFSDM2LPEN_Pos (25U)
10402#define RCC_APB2LPENR_DFSDM2LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM2LPEN_Pos)
10403#define RCC_APB2LPENR_DFSDM2LPEN RCC_APB2LPENR_DFSDM2LPEN_Msk
10404
10405/******************** Bit definition for RCC_BDCR register ******************/
10406#define RCC_BDCR_LSEON_Pos (0U)
10407#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
10408#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
10409#define RCC_BDCR_LSERDY_Pos (1U)
10410#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
10411#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
10412#define RCC_BDCR_LSEBYP_Pos (2U)
10413#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
10414#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
10415#define RCC_BDCR_LSEMOD_Pos (3U)
10416#define RCC_BDCR_LSEMOD_Msk (0x1UL << RCC_BDCR_LSEMOD_Pos)
10417#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
10418
10419#define RCC_BDCR_RTCSEL_Pos (8U)
10420#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
10421#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
10422#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
10423#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
10424
10425#define RCC_BDCR_RTCEN_Pos (15U)
10426#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
10427#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
10428#define RCC_BDCR_BDRST_Pos (16U)
10429#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
10430#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
10431
10432/******************** Bit definition for RCC_CSR register *******************/
10433#define RCC_CSR_LSION_Pos (0U)
10434#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
10435#define RCC_CSR_LSION RCC_CSR_LSION_Msk
10436#define RCC_CSR_LSIRDY_Pos (1U)
10437#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
10438#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
10439#define RCC_CSR_RMVF_Pos (24U)
10440#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
10441#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
10442#define RCC_CSR_BORRSTF_Pos (25U)
10443#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
10444#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
10445#define RCC_CSR_PINRSTF_Pos (26U)
10446#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
10447#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
10448#define RCC_CSR_PORRSTF_Pos (27U)
10449#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
10450#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
10451#define RCC_CSR_SFTRSTF_Pos (28U)
10452#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
10453#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
10454#define RCC_CSR_IWDGRSTF_Pos (29U)
10455#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
10456#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
10457#define RCC_CSR_WWDGRSTF_Pos (30U)
10458#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
10459#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
10460#define RCC_CSR_LPWRRSTF_Pos (31U)
10461#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
10462#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
10463/* Legacy defines */
10464#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
10465#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
10466
10467/******************** Bit definition for RCC_SSCGR register *****************/
10468#define RCC_SSCGR_MODPER_Pos (0U)
10469#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
10470#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
10471#define RCC_SSCGR_INCSTEP_Pos (13U)
10472#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
10473#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
10474#define RCC_SSCGR_SPREADSEL_Pos (30U)
10475#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
10476#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
10477#define RCC_SSCGR_SSCGEN_Pos (31U)
10478#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
10479#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
10480
10481/******************** Bit definition for RCC_PLLI2SCFGR register ************/
10482#define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
10483#define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FUL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10484#define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
10485#define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10486#define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10487#define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10488#define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10489#define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10490#define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
10491
10492#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
10493#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10494#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
10495#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10496#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10497#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10498#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10499#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10500#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10501#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10502#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10503#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10504
10505#define RCC_PLLI2SCFGR_PLLI2SSRC_Pos (22U)
10506#define RCC_PLLI2SCFGR_PLLI2SSRC_Msk (0x1UL << RCC_PLLI2SCFGR_PLLI2SSRC_Pos)
10507#define RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC_Msk
10508#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
10509#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10510#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
10511#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10512#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10513#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10514#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10515#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
10516#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10517#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
10518#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10519#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10520#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10521
10522
10523
10524/******************** Bit definition for RCC_DCKCFGR register ***************/
10525#define RCC_DCKCFGR_PLLI2SDIVR_Pos (0U)
10526#define RCC_DCKCFGR_PLLI2SDIVR_Msk (0x1FUL << RCC_DCKCFGR_PLLI2SDIVR_Pos)
10527#define RCC_DCKCFGR_PLLI2SDIVR RCC_DCKCFGR_PLLI2SDIVR_Msk
10528#define RCC_DCKCFGR_PLLI2SDIVR_0 (0x01UL << RCC_DCKCFGR_PLLI2SDIVR_Pos)
10529#define RCC_DCKCFGR_PLLI2SDIVR_1 (0x02UL << RCC_DCKCFGR_PLLI2SDIVR_Pos)
10530#define RCC_DCKCFGR_PLLI2SDIVR_2 (0x04UL << RCC_DCKCFGR_PLLI2SDIVR_Pos)
10531#define RCC_DCKCFGR_PLLI2SDIVR_3 (0x08UL << RCC_DCKCFGR_PLLI2SDIVR_Pos)
10532#define RCC_DCKCFGR_PLLI2SDIVR_4 (0x10UL << RCC_DCKCFGR_PLLI2SDIVR_Pos)
10533
10534#define RCC_DCKCFGR_PLLDIVR_Pos (8U)
10535#define RCC_DCKCFGR_PLLDIVR_Msk (0x1FUL << RCC_DCKCFGR_PLLDIVR_Pos)
10536#define RCC_DCKCFGR_PLLDIVR RCC_DCKCFGR_PLLDIVR_Msk
10537#define RCC_DCKCFGR_PLLDIVR_0 (0x01UL << RCC_DCKCFGR_PLLDIVR_Pos)
10538#define RCC_DCKCFGR_PLLDIVR_1 (0x02UL << RCC_DCKCFGR_PLLDIVR_Pos)
10539#define RCC_DCKCFGR_PLLDIVR_2 (0x04UL << RCC_DCKCFGR_PLLDIVR_Pos)
10540#define RCC_DCKCFGR_PLLDIVR_3 (0x08UL << RCC_DCKCFGR_PLLDIVR_Pos)
10541#define RCC_DCKCFGR_PLLDIVR_4 (0x10UL << RCC_DCKCFGR_PLLDIVR_Pos)
10542
10543#define RCC_DCKCFGR_CKDFSDM2ASEL_Pos (14U)
10544#define RCC_DCKCFGR_CKDFSDM2ASEL_Msk (0x1UL << RCC_DCKCFGR_CKDFSDM2ASEL_Pos)
10545#define RCC_DCKCFGR_CKDFSDM2ASEL RCC_DCKCFGR_CKDFSDM2ASEL_Msk
10546#define RCC_DCKCFGR_CKDFSDM1ASEL_Pos (15U)
10547#define RCC_DCKCFGR_CKDFSDM1ASEL_Msk (0x1UL << RCC_DCKCFGR_CKDFSDM1ASEL_Pos)
10548#define RCC_DCKCFGR_CKDFSDM1ASEL RCC_DCKCFGR_CKDFSDM1ASEL_Msk
10549
10550/*
10551 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
10552 */
10553#define RCC_SAI1A_PLLSOURCE_SUPPORT
10554#define RCC_SAI1B_PLLSOURCE_SUPPORT
10555
10556#define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
10557#define RCC_DCKCFGR_SAI1ASRC_Msk (0x3UL << RCC_DCKCFGR_SAI1ASRC_Pos)
10558#define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
10559#define RCC_DCKCFGR_SAI1ASRC_0 (0x1UL << RCC_DCKCFGR_SAI1ASRC_Pos)
10560#define RCC_DCKCFGR_SAI1ASRC_1 (0x2UL << RCC_DCKCFGR_SAI1ASRC_Pos)
10561#define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
10562#define RCC_DCKCFGR_SAI1BSRC_Msk (0x3UL << RCC_DCKCFGR_SAI1BSRC_Pos)
10563#define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
10564#define RCC_DCKCFGR_SAI1BSRC_0 (0x1UL << RCC_DCKCFGR_SAI1BSRC_Pos)
10565#define RCC_DCKCFGR_SAI1BSRC_1 (0x2UL << RCC_DCKCFGR_SAI1BSRC_Pos)
10566#define RCC_DCKCFGR_TIMPRE_Pos (24U)
10567#define RCC_DCKCFGR_TIMPRE_Msk (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)
10568#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
10569#define RCC_DCKCFGR_I2S1SRC_Pos (25U)
10570#define RCC_DCKCFGR_I2S1SRC_Msk (0x3UL << RCC_DCKCFGR_I2S1SRC_Pos)
10571#define RCC_DCKCFGR_I2S1SRC RCC_DCKCFGR_I2S1SRC_Msk
10572#define RCC_DCKCFGR_I2S1SRC_0 (0x1UL << RCC_DCKCFGR_I2S1SRC_Pos)
10573#define RCC_DCKCFGR_I2S1SRC_1 (0x2UL << RCC_DCKCFGR_I2S1SRC_Pos)
10574
10575#define RCC_DCKCFGR_I2S2SRC_Pos (27U)
10576#define RCC_DCKCFGR_I2S2SRC_Msk (0x3UL << RCC_DCKCFGR_I2S2SRC_Pos)
10577#define RCC_DCKCFGR_I2S2SRC RCC_DCKCFGR_I2S2SRC_Msk
10578#define RCC_DCKCFGR_I2S2SRC_0 (0x1UL << RCC_DCKCFGR_I2S2SRC_Pos)
10579#define RCC_DCKCFGR_I2S2SRC_1 (0x2UL << RCC_DCKCFGR_I2S2SRC_Pos)
10580#define RCC_DCKCFGR_CKDFSDM1SEL_Pos (31U)
10581#define RCC_DCKCFGR_CKDFSDM1SEL_Msk (0x1UL << RCC_DCKCFGR_CKDFSDM1SEL_Pos)
10582#define RCC_DCKCFGR_CKDFSDM1SEL RCC_DCKCFGR_CKDFSDM1SEL_Msk
10583
10584/******************** Bit definition for RCC_CKGATENR register ***************/
10585#define RCC_CKGATENR_AHB2APB1_CKEN_Pos (0U)
10586#define RCC_CKGATENR_AHB2APB1_CKEN_Msk (0x1UL << RCC_CKGATENR_AHB2APB1_CKEN_Pos)
10587#define RCC_CKGATENR_AHB2APB1_CKEN RCC_CKGATENR_AHB2APB1_CKEN_Msk
10588#define RCC_CKGATENR_AHB2APB2_CKEN_Pos (1U)
10589#define RCC_CKGATENR_AHB2APB2_CKEN_Msk (0x1UL << RCC_CKGATENR_AHB2APB2_CKEN_Pos)
10590#define RCC_CKGATENR_AHB2APB2_CKEN RCC_CKGATENR_AHB2APB2_CKEN_Msk
10591#define RCC_CKGATENR_CM4DBG_CKEN_Pos (2U)
10592#define RCC_CKGATENR_CM4DBG_CKEN_Msk (0x1UL << RCC_CKGATENR_CM4DBG_CKEN_Pos)
10593#define RCC_CKGATENR_CM4DBG_CKEN RCC_CKGATENR_CM4DBG_CKEN_Msk
10594#define RCC_CKGATENR_SPARE_CKEN_Pos (3U)
10595#define RCC_CKGATENR_SPARE_CKEN_Msk (0x1UL << RCC_CKGATENR_SPARE_CKEN_Pos)
10596#define RCC_CKGATENR_SPARE_CKEN RCC_CKGATENR_SPARE_CKEN_Msk
10597#define RCC_CKGATENR_SRAM_CKEN_Pos (4U)
10598#define RCC_CKGATENR_SRAM_CKEN_Msk (0x1UL << RCC_CKGATENR_SRAM_CKEN_Pos)
10599#define RCC_CKGATENR_SRAM_CKEN RCC_CKGATENR_SRAM_CKEN_Msk
10600#define RCC_CKGATENR_FLITF_CKEN_Pos (5U)
10601#define RCC_CKGATENR_FLITF_CKEN_Msk (0x1UL << RCC_CKGATENR_FLITF_CKEN_Pos)
10602#define RCC_CKGATENR_FLITF_CKEN RCC_CKGATENR_FLITF_CKEN_Msk
10603#define RCC_CKGATENR_RCC_CKEN_Pos (6U)
10604#define RCC_CKGATENR_RCC_CKEN_Msk (0x1UL << RCC_CKGATENR_RCC_CKEN_Pos)
10605#define RCC_CKGATENR_RCC_CKEN RCC_CKGATENR_RCC_CKEN_Msk
10606#define RCC_CKGATENR_RCC_EVTCTL_Pos (7U)
10607#define RCC_CKGATENR_RCC_EVTCTL_Msk (0x1UL << RCC_CKGATENR_RCC_EVTCTL_Pos)
10608#define RCC_CKGATENR_RCC_EVTCTL RCC_CKGATENR_RCC_EVTCTL_Msk
10609
10610/******************** Bit definition for RCC_DCKCFGR2 register ***************/
10611#define RCC_DCKCFGR2_FMPI2C1SEL_Pos (22U)
10612#define RCC_DCKCFGR2_FMPI2C1SEL_Msk (0x3UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos)
10613#define RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_Msk
10614#define RCC_DCKCFGR2_FMPI2C1SEL_0 (0x1UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos)
10615#define RCC_DCKCFGR2_FMPI2C1SEL_1 (0x2UL << RCC_DCKCFGR2_FMPI2C1SEL_Pos)
10616#define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
10617#define RCC_DCKCFGR2_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos)
10618#define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
10619#define RCC_DCKCFGR2_SDIOSEL_Pos (28U)
10620#define RCC_DCKCFGR2_SDIOSEL_Msk (0x1UL << RCC_DCKCFGR2_SDIOSEL_Pos)
10621#define RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_Msk
10622#define RCC_DCKCFGR2_LPTIM1SEL_Pos (30U)
10623#define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
10624#define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
10625#define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
10626#define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
10627
10628
10629/******************************************************************************/
10630/* */
10631/* Advanced Encryption Standard (AES) */
10632/* */
10633/******************************************************************************/
10634/******************* Bit definition for AES_CR register *********************/
10635#define AES_CR_EN ((uint32_t)0x00000001U)
10636#define AES_CR_DATATYPE ((uint32_t)0x00000006U)
10637#define AES_CR_DATATYPE_0 ((uint32_t)0x00000002U)
10638#define AES_CR_DATATYPE_1 ((uint32_t)0x00000004U)
10639
10640#define AES_CR_MODE ((uint32_t)0x00000018U)
10641#define AES_CR_MODE_0 ((uint32_t)0x00000008U)
10642#define AES_CR_MODE_1 ((uint32_t)0x00000010U)
10643
10644#define AES_CR_CHMOD ((uint32_t)0x00010060U)
10645#define AES_CR_CHMOD_0 ((uint32_t)0x00000020U)
10646#define AES_CR_CHMOD_1 ((uint32_t)0x00000040U)
10647#define AES_CR_CHMOD_2 ((uint32_t)0x00010000U)
10648
10649#define AES_CR_CCFC ((uint32_t)0x00000080U)
10650#define AES_CR_ERRC ((uint32_t)0x00000100U)
10651#define AES_CR_CCFIE ((uint32_t)0x00000200U)
10652#define AES_CR_ERRIE ((uint32_t)0x00000400U)
10653#define AES_CR_DMAINEN ((uint32_t)0x00000800U)
10654#define AES_CR_DMAOUTEN ((uint32_t)0x00001000U)
10655
10656#define AES_CR_GCMPH ((uint32_t)0x00006000U)
10657#define AES_CR_GCMPH_0 ((uint32_t)0x00002000U)
10658#define AES_CR_GCMPH_1 ((uint32_t)0x00004000U)
10659
10660#define AES_CR_KEYSIZE ((uint32_t)0x00040000U)
10661
10662/******************* Bit definition for AES_SR register *********************/
10663#define AES_SR_CCF ((uint32_t)0x00000001U)
10664#define AES_SR_RDERR ((uint32_t)0x00000002U)
10665#define AES_SR_WRERR ((uint32_t)0x00000004U)
10666#define AES_SR_BUSY ((uint32_t)0x00000008U)
10667
10668/******************* Bit definition for AES_DINR register *******************/
10669#define AES_DINR ((uint32_t)0xFFFFFFFFU)
10670
10671/******************* Bit definition for AES_DOUTR register ******************/
10672#define AES_DOUTR ((uint32_t)0xFFFFFFFFU)
10673
10674/******************* Bit definition for AES_KEYR0 register ******************/
10675#define AES_KEYR0 ((uint32_t)0xFFFFFFFFU)
10676
10677/******************* Bit definition for AES_KEYR1 register ******************/
10678#define AES_KEYR1 ((uint32_t)0xFFFFFFFFU)
10679
10680/******************* Bit definition for AES_KEYR2 register ******************/
10681#define AES_KEYR2 ((uint32_t)0xFFFFFFFFU)
10682
10683/******************* Bit definition for AES_KEYR3 register ******************/
10684#define AES_KEYR3 ((uint32_t)0xFFFFFFFFU)
10685
10686/******************* Bit definition for AES_KEYR4 register ******************/
10687#define AES_KEYR4 ((uint32_t)0xFFFFFFFFU)
10688
10689/******************* Bit definition for AES_KEYR5 register ******************/
10690#define AES_KEYR5 ((uint32_t)0xFFFFFFFFU)
10691
10692/******************* Bit definition for AES_KEYR6 register ******************/
10693#define AES_KEYR6 ((uint32_t)0xFFFFFFFFU)
10694
10695/******************* Bit definition for AES_KEYR7 register ******************/
10696#define AES_KEYR7 ((uint32_t)0xFFFFFFFFU)
10697
10698/******************* Bit definition for AES_IVR0 register ******************/
10699#define AES_IVR0 ((uint32_t)0xFFFFFFFFU)
10700
10701/******************* Bit definition for AES_IVR1 register ******************/
10702#define AES_IVR1 ((uint32_t)0xFFFFFFFFU)
10703
10704/******************* Bit definition for AES_IVR2 register ******************/
10705#define AES_IVR2 ((uint32_t)0xFFFFFFFFU)
10706
10707/******************* Bit definition for AES_IVR3 register ******************/
10708#define AES_IVR3 ((uint32_t)0xFFFFFFFFU)
10709
10710/******************* Bit definition for AES_SUSP0R register ******************/
10711#define AES_SUSP0R ((uint32_t)0xFFFFFFFFU)
10712
10713/******************* Bit definition for AES_SUSP1R register ******************/
10714#define AES_SUSP1R ((uint32_t)0xFFFFFFFFU)
10715
10716/******************* Bit definition for AES_SUSP2R register ******************/
10717#define AES_SUSP2R ((uint32_t)0xFFFFFFFFU)
10718
10719/******************* Bit definition for AES_SUSP3R register ******************/
10720#define AES_SUSP3R ((uint32_t)0xFFFFFFFFU)
10721
10722/******************* Bit definition for AES_SUSP4R register ******************/
10723#define AES_SUSP4R ((uint32_t)0xFFFFFFFFU)
10724
10725/******************* Bit definition for AES_SUSP5R register ******************/
10726#define AES_SUSP5R ((uint32_t)0xFFFFFFFFU)
10727
10728/******************* Bit definition for AES_SUSP6R register ******************/
10729#define AES_SUSP6R ((uint32_t)0xFFFFFFFFU)
10730
10731/******************* Bit definition for AES_SUSP7R register ******************/
10732#define AES_SUSP7R ((uint32_t)0xFFFFFFFFU)
10733
10734/******************************************************************************/
10735/* */
10736/* RNG */
10737/* */
10738/******************************************************************************/
10739/******************** Bits definition for RNG_CR register *******************/
10740#define RNG_CR_RNGEN_Pos (2U)
10741#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
10742#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
10743#define RNG_CR_IE_Pos (3U)
10744#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
10745#define RNG_CR_IE RNG_CR_IE_Msk
10746
10747/******************** Bits definition for RNG_SR register *******************/
10748#define RNG_SR_DRDY_Pos (0U)
10749#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
10750#define RNG_SR_DRDY RNG_SR_DRDY_Msk
10751#define RNG_SR_CECS_Pos (1U)
10752#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
10753#define RNG_SR_CECS RNG_SR_CECS_Msk
10754#define RNG_SR_SECS_Pos (2U)
10755#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
10756#define RNG_SR_SECS RNG_SR_SECS_Msk
10757#define RNG_SR_CEIS_Pos (5U)
10758#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
10759#define RNG_SR_CEIS RNG_SR_CEIS_Msk
10760#define RNG_SR_SEIS_Pos (6U)
10761#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
10762#define RNG_SR_SEIS RNG_SR_SEIS_Msk
10763
10764/******************************************************************************/
10765/* */
10766/* Real-Time Clock (RTC) */
10767/* */
10768/******************************************************************************/
10769/******************** Bits definition for RTC_TR register *******************/
10770#define RTC_TR_PM_Pos (22U)
10771#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
10772#define RTC_TR_PM RTC_TR_PM_Msk
10773#define RTC_TR_HT_Pos (20U)
10774#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
10775#define RTC_TR_HT RTC_TR_HT_Msk
10776#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
10777#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
10778#define RTC_TR_HU_Pos (16U)
10779#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
10780#define RTC_TR_HU RTC_TR_HU_Msk
10781#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
10782#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
10783#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
10784#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
10785#define RTC_TR_MNT_Pos (12U)
10786#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
10787#define RTC_TR_MNT RTC_TR_MNT_Msk
10788#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
10789#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
10790#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
10791#define RTC_TR_MNU_Pos (8U)
10792#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
10793#define RTC_TR_MNU RTC_TR_MNU_Msk
10794#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
10795#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
10796#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
10797#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
10798#define RTC_TR_ST_Pos (4U)
10799#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
10800#define RTC_TR_ST RTC_TR_ST_Msk
10801#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
10802#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
10803#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
10804#define RTC_TR_SU_Pos (0U)
10805#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
10806#define RTC_TR_SU RTC_TR_SU_Msk
10807#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
10808#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
10809#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
10810#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
10811
10812/******************** Bits definition for RTC_DR register *******************/
10813#define RTC_DR_YT_Pos (20U)
10814#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
10815#define RTC_DR_YT RTC_DR_YT_Msk
10816#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
10817#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
10818#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
10819#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
10820#define RTC_DR_YU_Pos (16U)
10821#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
10822#define RTC_DR_YU RTC_DR_YU_Msk
10823#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
10824#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
10825#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
10826#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
10827#define RTC_DR_WDU_Pos (13U)
10828#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
10829#define RTC_DR_WDU RTC_DR_WDU_Msk
10830#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
10831#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
10832#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
10833#define RTC_DR_MT_Pos (12U)
10834#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
10835#define RTC_DR_MT RTC_DR_MT_Msk
10836#define RTC_DR_MU_Pos (8U)
10837#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
10838#define RTC_DR_MU RTC_DR_MU_Msk
10839#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
10840#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
10841#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
10842#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
10843#define RTC_DR_DT_Pos (4U)
10844#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
10845#define RTC_DR_DT RTC_DR_DT_Msk
10846#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
10847#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
10848#define RTC_DR_DU_Pos (0U)
10849#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
10850#define RTC_DR_DU RTC_DR_DU_Msk
10851#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
10852#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
10853#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
10854#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
10855
10856/******************** Bits definition for RTC_CR register *******************/
10857#define RTC_CR_COE_Pos (23U)
10858#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
10859#define RTC_CR_COE RTC_CR_COE_Msk
10860#define RTC_CR_OSEL_Pos (21U)
10861#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
10862#define RTC_CR_OSEL RTC_CR_OSEL_Msk
10863#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
10864#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
10865#define RTC_CR_POL_Pos (20U)
10866#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
10867#define RTC_CR_POL RTC_CR_POL_Msk
10868#define RTC_CR_COSEL_Pos (19U)
10869#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
10870#define RTC_CR_COSEL RTC_CR_COSEL_Msk
10871#define RTC_CR_BKP_Pos (18U)
10872#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
10873#define RTC_CR_BKP RTC_CR_BKP_Msk
10874#define RTC_CR_SUB1H_Pos (17U)
10875#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
10876#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
10877#define RTC_CR_ADD1H_Pos (16U)
10878#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
10879#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
10880#define RTC_CR_TSIE_Pos (15U)
10881#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
10882#define RTC_CR_TSIE RTC_CR_TSIE_Msk
10883#define RTC_CR_WUTIE_Pos (14U)
10884#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
10885#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
10886#define RTC_CR_ALRBIE_Pos (13U)
10887#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
10888#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
10889#define RTC_CR_ALRAIE_Pos (12U)
10890#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
10891#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
10892#define RTC_CR_TSE_Pos (11U)
10893#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
10894#define RTC_CR_TSE RTC_CR_TSE_Msk
10895#define RTC_CR_WUTE_Pos (10U)
10896#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
10897#define RTC_CR_WUTE RTC_CR_WUTE_Msk
10898#define RTC_CR_ALRBE_Pos (9U)
10899#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
10900#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
10901#define RTC_CR_ALRAE_Pos (8U)
10902#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
10903#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
10904#define RTC_CR_DCE_Pos (7U)
10905#define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)
10906#define RTC_CR_DCE RTC_CR_DCE_Msk
10907#define RTC_CR_FMT_Pos (6U)
10908#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
10909#define RTC_CR_FMT RTC_CR_FMT_Msk
10910#define RTC_CR_BYPSHAD_Pos (5U)
10911#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
10912#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
10913#define RTC_CR_REFCKON_Pos (4U)
10914#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
10915#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
10916#define RTC_CR_TSEDGE_Pos (3U)
10917#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
10918#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
10919#define RTC_CR_WUCKSEL_Pos (0U)
10920#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
10921#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
10922#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
10923#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
10924#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
10925
10926/* Legacy defines */
10927#define RTC_CR_BCK RTC_CR_BKP
10928
10929/******************** Bits definition for RTC_ISR register ******************/
10930#define RTC_ISR_RECALPF_Pos (16U)
10931#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
10932#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
10933#define RTC_ISR_TAMP1F_Pos (13U)
10934#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
10935#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
10936#define RTC_ISR_TAMP2F_Pos (14U)
10937#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
10938#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
10939#define RTC_ISR_TSOVF_Pos (12U)
10940#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
10941#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
10942#define RTC_ISR_TSF_Pos (11U)
10943#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
10944#define RTC_ISR_TSF RTC_ISR_TSF_Msk
10945#define RTC_ISR_WUTF_Pos (10U)
10946#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
10947#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
10948#define RTC_ISR_ALRBF_Pos (9U)
10949#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
10950#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
10951#define RTC_ISR_ALRAF_Pos (8U)
10952#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
10953#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
10954#define RTC_ISR_INIT_Pos (7U)
10955#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
10956#define RTC_ISR_INIT RTC_ISR_INIT_Msk
10957#define RTC_ISR_INITF_Pos (6U)
10958#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
10959#define RTC_ISR_INITF RTC_ISR_INITF_Msk
10960#define RTC_ISR_RSF_Pos (5U)
10961#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
10962#define RTC_ISR_RSF RTC_ISR_RSF_Msk
10963#define RTC_ISR_INITS_Pos (4U)
10964#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
10965#define RTC_ISR_INITS RTC_ISR_INITS_Msk
10966#define RTC_ISR_SHPF_Pos (3U)
10967#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
10968#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
10969#define RTC_ISR_WUTWF_Pos (2U)
10970#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
10971#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
10972#define RTC_ISR_ALRBWF_Pos (1U)
10973#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
10974#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
10975#define RTC_ISR_ALRAWF_Pos (0U)
10976#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
10977#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
10978
10979/******************** Bits definition for RTC_PRER register *****************/
10980#define RTC_PRER_PREDIV_A_Pos (16U)
10981#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
10982#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
10983#define RTC_PRER_PREDIV_S_Pos (0U)
10984#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
10985#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
10986
10987/******************** Bits definition for RTC_WUTR register *****************/
10988#define RTC_WUTR_WUT_Pos (0U)
10989#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
10990#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
10991
10992/******************** Bits definition for RTC_CALIBR register ***************/
10993#define RTC_CALIBR_DCS_Pos (7U)
10994#define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)
10995#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
10996#define RTC_CALIBR_DC_Pos (0U)
10997#define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)
10998#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
10999
11000/******************** Bits definition for RTC_ALRMAR register ***************/
11001#define RTC_ALRMAR_MSK4_Pos (31U)
11002#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
11003#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
11004#define RTC_ALRMAR_WDSEL_Pos (30U)
11005#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
11006#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
11007#define RTC_ALRMAR_DT_Pos (28U)
11008#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
11009#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
11010#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
11011#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
11012#define RTC_ALRMAR_DU_Pos (24U)
11013#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
11014#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
11015#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
11016#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
11017#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
11018#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
11019#define RTC_ALRMAR_MSK3_Pos (23U)
11020#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
11021#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
11022#define RTC_ALRMAR_PM_Pos (22U)
11023#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
11024#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
11025#define RTC_ALRMAR_HT_Pos (20U)
11026#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
11027#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
11028#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
11029#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
11030#define RTC_ALRMAR_HU_Pos (16U)
11031#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
11032#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
11033#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
11034#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
11035#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
11036#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
11037#define RTC_ALRMAR_MSK2_Pos (15U)
11038#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
11039#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
11040#define RTC_ALRMAR_MNT_Pos (12U)
11041#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
11042#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
11043#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
11044#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
11045#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
11046#define RTC_ALRMAR_MNU_Pos (8U)
11047#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
11048#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
11049#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
11050#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
11051#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
11052#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
11053#define RTC_ALRMAR_MSK1_Pos (7U)
11054#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
11055#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
11056#define RTC_ALRMAR_ST_Pos (4U)
11057#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
11058#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
11059#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
11060#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
11061#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
11062#define RTC_ALRMAR_SU_Pos (0U)
11063#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
11064#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
11065#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
11066#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
11067#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
11068#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
11069
11070/******************** Bits definition for RTC_ALRMBR register ***************/
11071#define RTC_ALRMBR_MSK4_Pos (31U)
11072#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
11073#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
11074#define RTC_ALRMBR_WDSEL_Pos (30U)
11075#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
11076#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
11077#define RTC_ALRMBR_DT_Pos (28U)
11078#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
11079#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
11080#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
11081#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
11082#define RTC_ALRMBR_DU_Pos (24U)
11083#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
11084#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
11085#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
11086#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
11087#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
11088#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
11089#define RTC_ALRMBR_MSK3_Pos (23U)
11090#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
11091#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
11092#define RTC_ALRMBR_PM_Pos (22U)
11093#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
11094#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
11095#define RTC_ALRMBR_HT_Pos (20U)
11096#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
11097#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
11098#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
11099#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
11100#define RTC_ALRMBR_HU_Pos (16U)
11101#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
11102#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
11103#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
11104#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
11105#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
11106#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
11107#define RTC_ALRMBR_MSK2_Pos (15U)
11108#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
11109#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
11110#define RTC_ALRMBR_MNT_Pos (12U)
11111#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
11112#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
11113#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
11114#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
11115#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
11116#define RTC_ALRMBR_MNU_Pos (8U)
11117#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
11118#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
11119#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
11120#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
11121#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
11122#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
11123#define RTC_ALRMBR_MSK1_Pos (7U)
11124#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
11125#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
11126#define RTC_ALRMBR_ST_Pos (4U)
11127#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
11128#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
11129#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
11130#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
11131#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
11132#define RTC_ALRMBR_SU_Pos (0U)
11133#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
11134#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
11135#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
11136#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
11137#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
11138#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
11139
11140/******************** Bits definition for RTC_WPR register ******************/
11141#define RTC_WPR_KEY_Pos (0U)
11142#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
11143#define RTC_WPR_KEY RTC_WPR_KEY_Msk
11144
11145/******************** Bits definition for RTC_SSR register ******************/
11146#define RTC_SSR_SS_Pos (0U)
11147#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
11148#define RTC_SSR_SS RTC_SSR_SS_Msk
11149
11150/******************** Bits definition for RTC_SHIFTR register ***************/
11151#define RTC_SHIFTR_SUBFS_Pos (0U)
11152#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
11153#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
11154#define RTC_SHIFTR_ADD1S_Pos (31U)
11155#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
11156#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
11157
11158/******************** Bits definition for RTC_TSTR register *****************/
11159#define RTC_TSTR_PM_Pos (22U)
11160#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
11161#define RTC_TSTR_PM RTC_TSTR_PM_Msk
11162#define RTC_TSTR_HT_Pos (20U)
11163#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
11164#define RTC_TSTR_HT RTC_TSTR_HT_Msk
11165#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
11166#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
11167#define RTC_TSTR_HU_Pos (16U)
11168#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
11169#define RTC_TSTR_HU RTC_TSTR_HU_Msk
11170#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
11171#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
11172#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
11173#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
11174#define RTC_TSTR_MNT_Pos (12U)
11175#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
11176#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
11177#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
11178#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
11179#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
11180#define RTC_TSTR_MNU_Pos (8U)
11181#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
11182#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
11183#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
11184#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
11185#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
11186#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
11187#define RTC_TSTR_ST_Pos (4U)
11188#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
11189#define RTC_TSTR_ST RTC_TSTR_ST_Msk
11190#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
11191#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
11192#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
11193#define RTC_TSTR_SU_Pos (0U)
11194#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
11195#define RTC_TSTR_SU RTC_TSTR_SU_Msk
11196#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
11197#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
11198#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
11199#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
11200
11201/******************** Bits definition for RTC_TSDR register *****************/
11202#define RTC_TSDR_WDU_Pos (13U)
11203#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
11204#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
11205#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
11206#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
11207#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
11208#define RTC_TSDR_MT_Pos (12U)
11209#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
11210#define RTC_TSDR_MT RTC_TSDR_MT_Msk
11211#define RTC_TSDR_MU_Pos (8U)
11212#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
11213#define RTC_TSDR_MU RTC_TSDR_MU_Msk
11214#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
11215#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
11216#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
11217#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
11218#define RTC_TSDR_DT_Pos (4U)
11219#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
11220#define RTC_TSDR_DT RTC_TSDR_DT_Msk
11221#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
11222#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
11223#define RTC_TSDR_DU_Pos (0U)
11224#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
11225#define RTC_TSDR_DU RTC_TSDR_DU_Msk
11226#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
11227#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
11228#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
11229#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
11230
11231/******************** Bits definition for RTC_TSSSR register ****************/
11232#define RTC_TSSSR_SS_Pos (0U)
11233#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
11234#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
11235
11236/******************** Bits definition for RTC_CAL register *****************/
11237#define RTC_CALR_CALP_Pos (15U)
11238#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
11239#define RTC_CALR_CALP RTC_CALR_CALP_Msk
11240#define RTC_CALR_CALW8_Pos (14U)
11241#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
11242#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
11243#define RTC_CALR_CALW16_Pos (13U)
11244#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
11245#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
11246#define RTC_CALR_CALM_Pos (0U)
11247#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
11248#define RTC_CALR_CALM RTC_CALR_CALM_Msk
11249#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
11250#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
11251#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
11252#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
11253#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
11254#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
11255#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
11256#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
11257#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
11258
11259/******************** Bits definition for RTC_TAFCR register ****************/
11260#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
11261#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
11262#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
11263#define RTC_TAFCR_TSINSEL_Pos (17U)
11264#define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)
11265#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
11266#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
11267#define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
11268#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
11269#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
11270#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
11271#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
11272#define RTC_TAFCR_TAMPPRCH_Pos (13U)
11273#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
11274#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
11275#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
11276#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
11277#define RTC_TAFCR_TAMPFLT_Pos (11U)
11278#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
11279#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
11280#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
11281#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
11282#define RTC_TAFCR_TAMPFREQ_Pos (8U)
11283#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
11284#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
11285#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
11286#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
11287#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
11288#define RTC_TAFCR_TAMPTS_Pos (7U)
11289#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
11290#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
11291#define RTC_TAFCR_TAMP2TRG_Pos (4U)
11292#define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
11293#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
11294#define RTC_TAFCR_TAMP2E_Pos (3U)
11295#define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
11296#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
11297#define RTC_TAFCR_TAMPIE_Pos (2U)
11298#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
11299#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
11300#define RTC_TAFCR_TAMP1TRG_Pos (1U)
11301#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
11302#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
11303#define RTC_TAFCR_TAMP1E_Pos (0U)
11304#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
11305#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
11306
11307/* Legacy defines */
11308#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
11309
11310/******************** Bits definition for RTC_ALRMASSR register *************/
11311#define RTC_ALRMASSR_MASKSS_Pos (24U)
11312#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
11313#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
11314#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
11315#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
11316#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
11317#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
11318#define RTC_ALRMASSR_SS_Pos (0U)
11319#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
11320#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
11321
11322/******************** Bits definition for RTC_ALRMBSSR register *************/
11323#define RTC_ALRMBSSR_MASKSS_Pos (24U)
11324#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
11325#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
11326#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
11327#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
11328#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
11329#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
11330#define RTC_ALRMBSSR_SS_Pos (0U)
11331#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
11332#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
11333
11334/******************** Bits definition for RTC_BKP0R register ****************/
11335#define RTC_BKP0R_Pos (0U)
11336#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
11337#define RTC_BKP0R RTC_BKP0R_Msk
11338
11339/******************** Bits definition for RTC_BKP1R register ****************/
11340#define RTC_BKP1R_Pos (0U)
11341#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
11342#define RTC_BKP1R RTC_BKP1R_Msk
11343
11344/******************** Bits definition for RTC_BKP2R register ****************/
11345#define RTC_BKP2R_Pos (0U)
11346#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
11347#define RTC_BKP2R RTC_BKP2R_Msk
11348
11349/******************** Bits definition for RTC_BKP3R register ****************/
11350#define RTC_BKP3R_Pos (0U)
11351#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
11352#define RTC_BKP3R RTC_BKP3R_Msk
11353
11354/******************** Bits definition for RTC_BKP4R register ****************/
11355#define RTC_BKP4R_Pos (0U)
11356#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
11357#define RTC_BKP4R RTC_BKP4R_Msk
11358
11359/******************** Bits definition for RTC_BKP5R register ****************/
11360#define RTC_BKP5R_Pos (0U)
11361#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
11362#define RTC_BKP5R RTC_BKP5R_Msk
11363
11364/******************** Bits definition for RTC_BKP6R register ****************/
11365#define RTC_BKP6R_Pos (0U)
11366#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
11367#define RTC_BKP6R RTC_BKP6R_Msk
11368
11369/******************** Bits definition for RTC_BKP7R register ****************/
11370#define RTC_BKP7R_Pos (0U)
11371#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
11372#define RTC_BKP7R RTC_BKP7R_Msk
11373
11374/******************** Bits definition for RTC_BKP8R register ****************/
11375#define RTC_BKP8R_Pos (0U)
11376#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
11377#define RTC_BKP8R RTC_BKP8R_Msk
11378
11379/******************** Bits definition for RTC_BKP9R register ****************/
11380#define RTC_BKP9R_Pos (0U)
11381#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
11382#define RTC_BKP9R RTC_BKP9R_Msk
11383
11384/******************** Bits definition for RTC_BKP10R register ***************/
11385#define RTC_BKP10R_Pos (0U)
11386#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
11387#define RTC_BKP10R RTC_BKP10R_Msk
11388
11389/******************** Bits definition for RTC_BKP11R register ***************/
11390#define RTC_BKP11R_Pos (0U)
11391#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
11392#define RTC_BKP11R RTC_BKP11R_Msk
11393
11394/******************** Bits definition for RTC_BKP12R register ***************/
11395#define RTC_BKP12R_Pos (0U)
11396#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
11397#define RTC_BKP12R RTC_BKP12R_Msk
11398
11399/******************** Bits definition for RTC_BKP13R register ***************/
11400#define RTC_BKP13R_Pos (0U)
11401#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
11402#define RTC_BKP13R RTC_BKP13R_Msk
11403
11404/******************** Bits definition for RTC_BKP14R register ***************/
11405#define RTC_BKP14R_Pos (0U)
11406#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
11407#define RTC_BKP14R RTC_BKP14R_Msk
11408
11409/******************** Bits definition for RTC_BKP15R register ***************/
11410#define RTC_BKP15R_Pos (0U)
11411#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
11412#define RTC_BKP15R RTC_BKP15R_Msk
11413
11414/******************** Bits definition for RTC_BKP16R register ***************/
11415#define RTC_BKP16R_Pos (0U)
11416#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
11417#define RTC_BKP16R RTC_BKP16R_Msk
11418
11419/******************** Bits definition for RTC_BKP17R register ***************/
11420#define RTC_BKP17R_Pos (0U)
11421#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
11422#define RTC_BKP17R RTC_BKP17R_Msk
11423
11424/******************** Bits definition for RTC_BKP18R register ***************/
11425#define RTC_BKP18R_Pos (0U)
11426#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
11427#define RTC_BKP18R RTC_BKP18R_Msk
11428
11429/******************** Bits definition for RTC_BKP19R register ***************/
11430#define RTC_BKP19R_Pos (0U)
11431#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
11432#define RTC_BKP19R RTC_BKP19R_Msk
11433
11434/******************** Number of backup registers ******************************/
11435#define RTC_BKP_NUMBER 0x000000014U
11436
11437/******************************************************************************/
11438/* */
11439/* Serial Audio Interface */
11440/* */
11441/******************************************************************************/
11442/******************** Bit definition for SAI_GCR register *******************/
11443#define SAI_GCR_SYNCIN_Pos (0U)
11444#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
11445#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
11446#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
11447#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
11448
11449#define SAI_GCR_SYNCOUT_Pos (4U)
11450#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
11451#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
11452#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
11453#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
11454
11455/******************* Bit definition for SAI_xCR1 register *******************/
11456#define SAI_xCR1_MODE_Pos (0U)
11457#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
11458#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
11459#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
11460#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
11461
11462#define SAI_xCR1_PRTCFG_Pos (2U)
11463#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
11464#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
11465#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
11466#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
11467
11468#define SAI_xCR1_DS_Pos (5U)
11469#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
11470#define SAI_xCR1_DS SAI_xCR1_DS_Msk
11471#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
11472#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
11473#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
11474
11475#define SAI_xCR1_LSBFIRST_Pos (8U)
11476#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
11477#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
11478#define SAI_xCR1_CKSTR_Pos (9U)
11479#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
11480#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
11481
11482#define SAI_xCR1_SYNCEN_Pos (10U)
11483#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
11484#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
11485#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
11486#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
11487
11488#define SAI_xCR1_MONO_Pos (12U)
11489#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
11490#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
11491#define SAI_xCR1_OUTDRIV_Pos (13U)
11492#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
11493#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
11494#define SAI_xCR1_SAIEN_Pos (16U)
11495#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
11496#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
11497#define SAI_xCR1_DMAEN_Pos (17U)
11498#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
11499#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
11500#define SAI_xCR1_NODIV_Pos (19U)
11501#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
11502#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
11503
11504#define SAI_xCR1_MCKDIV_Pos (20U)
11505#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos)
11506#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
11507#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos)
11508#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos)
11509#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos)
11510#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos)
11511
11512/******************* Bit definition for SAI_xCR2 register *******************/
11513#define SAI_xCR2_FTH_Pos (0U)
11514#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
11515#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
11516#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
11517#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
11518#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
11519
11520#define SAI_xCR2_FFLUSH_Pos (3U)
11521#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
11522#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
11523#define SAI_xCR2_TRIS_Pos (4U)
11524#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
11525#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
11526#define SAI_xCR2_MUTE_Pos (5U)
11527#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
11528#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
11529#define SAI_xCR2_MUTEVAL_Pos (6U)
11530#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
11531#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
11532
11533#define SAI_xCR2_MUTECNT_Pos (7U)
11534#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
11535#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
11536#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
11537#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
11538#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
11539#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
11540#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
11541#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
11542
11543#define SAI_xCR2_CPL_Pos (13U)
11544#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
11545#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
11546
11547#define SAI_xCR2_COMP_Pos (14U)
11548#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
11549#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
11550#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
11551#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
11552
11553/****************** Bit definition for SAI_xFRCR register *******************/
11554#define SAI_xFRCR_FRL_Pos (0U)
11555#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
11556#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
11557#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
11558#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
11559#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
11560#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
11561#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
11562#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
11563#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
11564#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
11565
11566#define SAI_xFRCR_FSALL_Pos (8U)
11567#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
11568#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
11569#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
11570#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
11571#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
11572#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
11573#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
11574#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
11575#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
11576
11577#define SAI_xFRCR_FSDEF_Pos (16U)
11578#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
11579#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
11580#define SAI_xFRCR_FSPOL_Pos (17U)
11581#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
11582#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
11583#define SAI_xFRCR_FSOFF_Pos (18U)
11584#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
11585#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
11586/* Legacy defines */
11587#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
11588
11589/****************** Bit definition for SAI_xSLOTR register *******************/
11590#define SAI_xSLOTR_FBOFF_Pos (0U)
11591#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
11592#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
11593#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
11594#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
11595#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
11596#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
11597#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
11598
11599#define SAI_xSLOTR_SLOTSZ_Pos (6U)
11600#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
11601#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
11602#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
11603#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
11604
11605#define SAI_xSLOTR_NBSLOT_Pos (8U)
11606#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
11607#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
11608#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
11609#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
11610#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
11611#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
11612
11613#define SAI_xSLOTR_SLOTEN_Pos (16U)
11614#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
11615#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
11616
11617/******************* Bit definition for SAI_xIMR register *******************/
11618#define SAI_xIMR_OVRUDRIE_Pos (0U)
11619#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
11620#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
11621#define SAI_xIMR_MUTEDETIE_Pos (1U)
11622#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
11623#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
11624#define SAI_xIMR_WCKCFGIE_Pos (2U)
11625#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
11626#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
11627#define SAI_xIMR_FREQIE_Pos (3U)
11628#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
11629#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
11630#define SAI_xIMR_CNRDYIE_Pos (4U)
11631#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
11632#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
11633#define SAI_xIMR_AFSDETIE_Pos (5U)
11634#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
11635#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
11636#define SAI_xIMR_LFSDETIE_Pos (6U)
11637#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
11638#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
11639
11640/******************** Bit definition for SAI_xSR register *******************/
11641#define SAI_xSR_OVRUDR_Pos (0U)
11642#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
11643#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
11644#define SAI_xSR_MUTEDET_Pos (1U)
11645#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
11646#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
11647#define SAI_xSR_WCKCFG_Pos (2U)
11648#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
11649#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
11650#define SAI_xSR_FREQ_Pos (3U)
11651#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
11652#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
11653#define SAI_xSR_CNRDY_Pos (4U)
11654#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
11655#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
11656#define SAI_xSR_AFSDET_Pos (5U)
11657#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
11658#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
11659#define SAI_xSR_LFSDET_Pos (6U)
11660#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
11661#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
11662
11663#define SAI_xSR_FLVL_Pos (16U)
11664#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
11665#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
11666#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
11667#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
11668#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
11669
11670/****************** Bit definition for SAI_xCLRFR register ******************/
11671#define SAI_xCLRFR_COVRUDR_Pos (0U)
11672#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
11673#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
11674#define SAI_xCLRFR_CMUTEDET_Pos (1U)
11675#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
11676#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
11677#define SAI_xCLRFR_CWCKCFG_Pos (2U)
11678#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
11679#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
11680#define SAI_xCLRFR_CFREQ_Pos (3U)
11681#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
11682#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
11683#define SAI_xCLRFR_CCNRDY_Pos (4U)
11684#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
11685#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
11686#define SAI_xCLRFR_CAFSDET_Pos (5U)
11687#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
11688#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
11689#define SAI_xCLRFR_CLFSDET_Pos (6U)
11690#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
11691#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
11692
11693/****************** Bit definition for SAI_xDR register ******************/
11694#define SAI_xDR_DATA_Pos (0U)
11695#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
11696#define SAI_xDR_DATA SAI_xDR_DATA_Msk
11697
11698
11699/******************************************************************************/
11700/* */
11701/* SD host Interface */
11702/* */
11703/******************************************************************************/
11704/****************** Bit definition for SDIO_POWER register ******************/
11705#define SDIO_POWER_PWRCTRL_Pos (0U)
11706#define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)
11707#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk
11708#define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)
11709#define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)
11710
11711/****************** Bit definition for SDIO_CLKCR register ******************/
11712#define SDIO_CLKCR_CLKDIV_Pos (0U)
11713#define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
11714#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk
11715#define SDIO_CLKCR_CLKEN_Pos (8U)
11716#define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)
11717#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk
11718#define SDIO_CLKCR_PWRSAV_Pos (9U)
11719#define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
11720#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk
11721#define SDIO_CLKCR_BYPASS_Pos (10U)
11722#define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)
11723#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk
11724
11725#define SDIO_CLKCR_WIDBUS_Pos (11U)
11726#define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
11727#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk
11728#define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
11729#define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
11730
11731#define SDIO_CLKCR_NEGEDGE_Pos (13U)
11732#define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
11733#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk
11734#define SDIO_CLKCR_HWFC_EN_Pos (14U)
11735#define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
11736#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk
11737
11738/******************* Bit definition for SDIO_ARG register *******************/
11739#define SDIO_ARG_CMDARG_Pos (0U)
11740#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
11741#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk
11742
11743/******************* Bit definition for SDIO_CMD register *******************/
11744#define SDIO_CMD_CMDINDEX_Pos (0U)
11745#define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
11746#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
11747
11748#define SDIO_CMD_WAITRESP_Pos (6U)
11749#define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)
11750#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk
11751#define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)
11752#define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)
11753
11754#define SDIO_CMD_WAITINT_Pos (8U)
11755#define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)
11756#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk
11757#define SDIO_CMD_WAITPEND_Pos (9U)
11758#define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)
11759#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk
11760#define SDIO_CMD_CPSMEN_Pos (10U)
11761#define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)
11762#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk
11763#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
11764#define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
11765#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk
11766
11767/***************** Bit definition for SDIO_RESPCMD register *****************/
11768#define SDIO_RESPCMD_RESPCMD_Pos (0U)
11769#define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
11770#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk
11771
11772/****************** Bit definition for SDIO_RESP0 register ******************/
11773#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
11774#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
11775#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk
11776
11777/****************** Bit definition for SDIO_RESP1 register ******************/
11778#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
11779#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
11780#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk
11781
11782/****************** Bit definition for SDIO_RESP2 register ******************/
11783#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
11784#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
11785#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk
11786
11787/****************** Bit definition for SDIO_RESP3 register ******************/
11788#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
11789#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
11790#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk
11791
11792/****************** Bit definition for SDIO_RESP4 register ******************/
11793#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
11794#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
11795#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk
11796
11797/****************** Bit definition for SDIO_DTIMER register *****************/
11798#define SDIO_DTIMER_DATATIME_Pos (0U)
11799#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
11800#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk
11801
11802/****************** Bit definition for SDIO_DLEN register *******************/
11803#define SDIO_DLEN_DATALENGTH_Pos (0U)
11804#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
11805#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk
11806
11807/****************** Bit definition for SDIO_DCTRL register ******************/
11808#define SDIO_DCTRL_DTEN_Pos (0U)
11809#define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)
11810#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk
11811#define SDIO_DCTRL_DTDIR_Pos (1U)
11812#define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)
11813#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk
11814#define SDIO_DCTRL_DTMODE_Pos (2U)
11815#define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)
11816#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk
11817#define SDIO_DCTRL_DMAEN_Pos (3U)
11818#define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)
11819#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk
11820
11821#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
11822#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11823#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk
11824#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11825#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11826#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11827#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
11828
11829#define SDIO_DCTRL_RWSTART_Pos (8U)
11830#define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)
11831#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk
11832#define SDIO_DCTRL_RWSTOP_Pos (9U)
11833#define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
11834#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk
11835#define SDIO_DCTRL_RWMOD_Pos (10U)
11836#define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)
11837#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk
11838#define SDIO_DCTRL_SDIOEN_Pos (11U)
11839#define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
11840#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk
11841
11842/****************** Bit definition for SDIO_DCOUNT register *****************/
11843#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
11844#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
11845#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk
11846
11847/****************** Bit definition for SDIO_STA register ********************/
11848#define SDIO_STA_CCRCFAIL_Pos (0U)
11849#define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)
11850#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk
11851#define SDIO_STA_DCRCFAIL_Pos (1U)
11852#define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)
11853#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk
11854#define SDIO_STA_CTIMEOUT_Pos (2U)
11855#define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)
11856#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk
11857#define SDIO_STA_DTIMEOUT_Pos (3U)
11858#define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)
11859#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk
11860#define SDIO_STA_TXUNDERR_Pos (4U)
11861#define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)
11862#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk
11863#define SDIO_STA_RXOVERR_Pos (5U)
11864#define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)
11865#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk
11866#define SDIO_STA_CMDREND_Pos (6U)
11867#define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)
11868#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk
11869#define SDIO_STA_CMDSENT_Pos (7U)
11870#define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)
11871#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk
11872#define SDIO_STA_DATAEND_Pos (8U)
11873#define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)
11874#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk
11875#define SDIO_STA_DBCKEND_Pos (10U)
11876#define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)
11877#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk
11878#define SDIO_STA_CMDACT_Pos (11U)
11879#define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)
11880#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk
11881#define SDIO_STA_TXACT_Pos (12U)
11882#define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)
11883#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk
11884#define SDIO_STA_RXACT_Pos (13U)
11885#define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)
11886#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk
11887#define SDIO_STA_TXFIFOHE_Pos (14U)
11888#define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)
11889#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk
11890#define SDIO_STA_RXFIFOHF_Pos (15U)
11891#define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)
11892#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk
11893#define SDIO_STA_TXFIFOF_Pos (16U)
11894#define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)
11895#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk
11896#define SDIO_STA_RXFIFOF_Pos (17U)
11897#define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)
11898#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk
11899#define SDIO_STA_TXFIFOE_Pos (18U)
11900#define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)
11901#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk
11902#define SDIO_STA_RXFIFOE_Pos (19U)
11903#define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)
11904#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk
11905#define SDIO_STA_TXDAVL_Pos (20U)
11906#define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)
11907#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk
11908#define SDIO_STA_RXDAVL_Pos (21U)
11909#define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)
11910#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk
11911#define SDIO_STA_SDIOIT_Pos (22U)
11912#define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)
11913#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk
11914
11915/******************* Bit definition for SDIO_ICR register *******************/
11916#define SDIO_ICR_CCRCFAILC_Pos (0U)
11917#define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
11918#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk
11919#define SDIO_ICR_DCRCFAILC_Pos (1U)
11920#define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
11921#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk
11922#define SDIO_ICR_CTIMEOUTC_Pos (2U)
11923#define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
11924#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk
11925#define SDIO_ICR_DTIMEOUTC_Pos (3U)
11926#define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
11927#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk
11928#define SDIO_ICR_TXUNDERRC_Pos (4U)
11929#define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
11930#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk
11931#define SDIO_ICR_RXOVERRC_Pos (5U)
11932#define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)
11933#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk
11934#define SDIO_ICR_CMDRENDC_Pos (6U)
11935#define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)
11936#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk
11937#define SDIO_ICR_CMDSENTC_Pos (7U)
11938#define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)
11939#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk
11940#define SDIO_ICR_DATAENDC_Pos (8U)
11941#define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)
11942#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk
11943#define SDIO_ICR_DBCKENDC_Pos (10U)
11944#define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)
11945#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk
11946#define SDIO_ICR_SDIOITC_Pos (22U)
11947#define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)
11948#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk
11949
11950/****************** Bit definition for SDIO_MASK register *******************/
11951#define SDIO_MASK_CCRCFAILIE_Pos (0U)
11952#define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
11953#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk
11954#define SDIO_MASK_DCRCFAILIE_Pos (1U)
11955#define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
11956#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk
11957#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
11958#define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
11959#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk
11960#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
11961#define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
11962#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk
11963#define SDIO_MASK_TXUNDERRIE_Pos (4U)
11964#define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
11965#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk
11966#define SDIO_MASK_RXOVERRIE_Pos (5U)
11967#define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
11968#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk
11969#define SDIO_MASK_CMDRENDIE_Pos (6U)
11970#define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
11971#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk
11972#define SDIO_MASK_CMDSENTIE_Pos (7U)
11973#define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
11974#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk
11975#define SDIO_MASK_DATAENDIE_Pos (8U)
11976#define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)
11977#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk
11978#define SDIO_MASK_DBCKENDIE_Pos (10U)
11979#define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
11980#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk
11981#define SDIO_MASK_CMDACTIE_Pos (11U)
11982#define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)
11983#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk
11984#define SDIO_MASK_TXACTIE_Pos (12U)
11985#define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)
11986#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk
11987#define SDIO_MASK_RXACTIE_Pos (13U)
11988#define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)
11989#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk
11990#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
11991#define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
11992#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk
11993#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
11994#define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
11995#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk
11996#define SDIO_MASK_TXFIFOFIE_Pos (16U)
11997#define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
11998#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk
11999#define SDIO_MASK_RXFIFOFIE_Pos (17U)
12000#define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
12001#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk
12002#define SDIO_MASK_TXFIFOEIE_Pos (18U)
12003#define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
12004#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk
12005#define SDIO_MASK_RXFIFOEIE_Pos (19U)
12006#define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
12007#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk
12008#define SDIO_MASK_TXDAVLIE_Pos (20U)
12009#define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
12010#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk
12011#define SDIO_MASK_RXDAVLIE_Pos (21U)
12012#define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
12013#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk
12014#define SDIO_MASK_SDIOITIE_Pos (22U)
12015#define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)
12016#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk
12017
12018/***************** Bit definition for SDIO_FIFOCNT register *****************/
12019#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
12020#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
12021#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk
12022
12023/****************** Bit definition for SDIO_FIFO register *******************/
12024#define SDIO_FIFO_FIFODATA_Pos (0U)
12025#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
12026#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk
12027
12028/******************************************************************************/
12029/* */
12030/* Serial Peripheral Interface */
12031/* */
12032/******************************************************************************/
12033#define SPI_I2S_FULLDUPLEX_SUPPORT
12034#define I2S_APB1_APB2_FEATURE
12035
12036/******************* Bit definition for SPI_CR1 register ********************/
12037#define SPI_CR1_CPHA_Pos (0U)
12038#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
12039#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
12040#define SPI_CR1_CPOL_Pos (1U)
12041#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
12042#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
12043#define SPI_CR1_MSTR_Pos (2U)
12044#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
12045#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
12046
12047#define SPI_CR1_BR_Pos (3U)
12048#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
12049#define SPI_CR1_BR SPI_CR1_BR_Msk
12050#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
12051#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
12052#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
12053
12054#define SPI_CR1_SPE_Pos (6U)
12055#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
12056#define SPI_CR1_SPE SPI_CR1_SPE_Msk
12057#define SPI_CR1_LSBFIRST_Pos (7U)
12058#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
12059#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
12060#define SPI_CR1_SSI_Pos (8U)
12061#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
12062#define SPI_CR1_SSI SPI_CR1_SSI_Msk
12063#define SPI_CR1_SSM_Pos (9U)
12064#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
12065#define SPI_CR1_SSM SPI_CR1_SSM_Msk
12066#define SPI_CR1_RXONLY_Pos (10U)
12067#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
12068#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
12069#define SPI_CR1_DFF_Pos (11U)
12070#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
12071#define SPI_CR1_DFF SPI_CR1_DFF_Msk
12072#define SPI_CR1_CRCNEXT_Pos (12U)
12073#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
12074#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
12075#define SPI_CR1_CRCEN_Pos (13U)
12076#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
12077#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
12078#define SPI_CR1_BIDIOE_Pos (14U)
12079#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
12080#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
12081#define SPI_CR1_BIDIMODE_Pos (15U)
12082#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
12083#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
12084
12085/******************* Bit definition for SPI_CR2 register ********************/
12086#define SPI_CR2_RXDMAEN_Pos (0U)
12087#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
12088#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
12089#define SPI_CR2_TXDMAEN_Pos (1U)
12090#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
12091#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
12092#define SPI_CR2_SSOE_Pos (2U)
12093#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
12094#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
12095#define SPI_CR2_FRF_Pos (4U)
12096#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
12097#define SPI_CR2_FRF SPI_CR2_FRF_Msk
12098#define SPI_CR2_ERRIE_Pos (5U)
12099#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
12100#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
12101#define SPI_CR2_RXNEIE_Pos (6U)
12102#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
12103#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
12104#define SPI_CR2_TXEIE_Pos (7U)
12105#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
12106#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
12107
12108/******************** Bit definition for SPI_SR register ********************/
12109#define SPI_SR_RXNE_Pos (0U)
12110#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
12111#define SPI_SR_RXNE SPI_SR_RXNE_Msk
12112#define SPI_SR_TXE_Pos (1U)
12113#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
12114#define SPI_SR_TXE SPI_SR_TXE_Msk
12115#define SPI_SR_CHSIDE_Pos (2U)
12116#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
12117#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
12118#define SPI_SR_UDR_Pos (3U)
12119#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
12120#define SPI_SR_UDR SPI_SR_UDR_Msk
12121#define SPI_SR_CRCERR_Pos (4U)
12122#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
12123#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
12124#define SPI_SR_MODF_Pos (5U)
12125#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
12126#define SPI_SR_MODF SPI_SR_MODF_Msk
12127#define SPI_SR_OVR_Pos (6U)
12128#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
12129#define SPI_SR_OVR SPI_SR_OVR_Msk
12130#define SPI_SR_BSY_Pos (7U)
12131#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
12132#define SPI_SR_BSY SPI_SR_BSY_Msk
12133#define SPI_SR_FRE_Pos (8U)
12134#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
12135#define SPI_SR_FRE SPI_SR_FRE_Msk
12136
12137/******************** Bit definition for SPI_DR register ********************/
12138#define SPI_DR_DR_Pos (0U)
12139#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
12140#define SPI_DR_DR SPI_DR_DR_Msk
12141
12142/******************* Bit definition for SPI_CRCPR register ******************/
12143#define SPI_CRCPR_CRCPOLY_Pos (0U)
12144#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
12145#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
12146
12147/****************** Bit definition for SPI_RXCRCR register ******************/
12148#define SPI_RXCRCR_RXCRC_Pos (0U)
12149#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
12150#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
12151
12152/****************** Bit definition for SPI_TXCRCR register ******************/
12153#define SPI_TXCRCR_TXCRC_Pos (0U)
12154#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
12155#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
12156
12157/****************** Bit definition for SPI_I2SCFGR register *****************/
12158#define SPI_I2SCFGR_CHLEN_Pos (0U)
12159#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
12160#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
12161
12162#define SPI_I2SCFGR_DATLEN_Pos (1U)
12163#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
12164#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
12165#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
12166#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
12167
12168#define SPI_I2SCFGR_CKPOL_Pos (3U)
12169#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
12170#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
12171
12172#define SPI_I2SCFGR_I2SSTD_Pos (4U)
12173#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
12174#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
12175#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
12176#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
12177
12178#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
12179#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
12180#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
12181
12182#define SPI_I2SCFGR_I2SCFG_Pos (8U)
12183#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
12184#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
12185#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
12186#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
12187
12188#define SPI_I2SCFGR_I2SE_Pos (10U)
12189#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
12190#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
12191#define SPI_I2SCFGR_I2SMOD_Pos (11U)
12192#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
12193#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
12194#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
12195#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)
12196#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk
12197
12198/****************** Bit definition for SPI_I2SPR register *******************/
12199#define SPI_I2SPR_I2SDIV_Pos (0U)
12200#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
12201#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
12202#define SPI_I2SPR_ODD_Pos (8U)
12203#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
12204#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
12205#define SPI_I2SPR_MCKOE_Pos (9U)
12206#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
12207#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
12208
12209/******************************************************************************/
12210/* */
12211/* SYSCFG */
12212/* */
12213/******************************************************************************/
12214/****************** Bit definition for SYSCFG_MEMRMP register ***************/
12215#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
12216#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
12217#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
12218#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
12219#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
12220/****************** Bit definition for SYSCFG_PMC register ******************/
12221#define SYSCFG_PMC_ADC1DC2_Pos (16U)
12222#define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)
12223#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk
12224
12225/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
12226#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
12227#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
12228#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
12229#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
12230#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
12231#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
12232#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
12233#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
12234#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
12235#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
12236#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
12237#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
12241#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
12242#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
12243#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
12244#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
12245#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
12246#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
12247#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
12248#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
12249
12253#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
12254#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
12255#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
12256#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
12257#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
12258#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
12259#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
12260#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
12261
12265#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
12266#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
12267#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
12268#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
12269#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
12270#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
12271#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
12272#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
12273
12277#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
12278#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
12279#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
12280#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
12281#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
12282#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
12283#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
12284#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
12285
12286/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
12287#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
12288#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
12289#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
12290#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
12291#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
12292#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
12293#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
12294#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
12295#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
12296#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
12297#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
12298#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
12299
12303#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
12304#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
12305#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
12306#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
12307#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
12308#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
12309#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
12310#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
12311
12315#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
12316#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
12317#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
12318#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
12319#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
12320#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
12321#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
12322#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
12323
12327#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
12328#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
12329#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
12330#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
12331#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
12332#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
12333#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
12334#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
12335
12339#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
12340#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
12341#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
12342#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
12343#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
12344#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
12345#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
12346#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
12347
12348/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
12349#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
12350#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
12351#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
12352#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
12353#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
12354#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
12355#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
12356#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
12357#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
12358#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
12359#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
12360#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
12361
12365#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
12366#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
12367#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
12368#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
12369#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
12370#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
12371#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
12372#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
12373
12377#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
12378#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
12379#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
12380#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
12381#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
12382#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
12383#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
12384#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
12385
12389#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
12390#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
12391#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
12392#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
12393#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
12394#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
12395#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
12396#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
12397
12401#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
12402#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
12403#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
12404#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
12405#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
12406#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
12407#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
12408#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
12409
12410/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
12411#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
12412#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
12413#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
12414#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
12415#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
12416#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
12417#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
12418#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
12419#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
12420#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
12421#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
12422#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
12423
12427#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
12428#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
12429#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
12430#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
12431#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
12432#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
12433#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
12434#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
12435
12439#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
12440#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
12441#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
12442#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
12443#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
12444#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
12445#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
12446#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
12447
12451#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
12452#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
12453#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
12454#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
12455#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
12456#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
12457#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
12458#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
12459
12463#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
12464#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
12465#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
12466#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
12467#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
12468#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
12469#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
12470#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
12471
12472/****************** Bit definition for SYSCFG_CMPCR register ****************/
12473#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
12474#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
12475#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
12476#define SYSCFG_CMPCR_READY_Pos (8U)
12477#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
12478#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
12479/****************** Bit definition for SYSCFG_CFGR register *****************/
12480#define SYSCFG_CFGR_FMPI2C1_SCL_Pos (0U)
12481#define SYSCFG_CFGR_FMPI2C1_SCL_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SCL_Pos)
12482#define SYSCFG_CFGR_FMPI2C1_SCL SYSCFG_CFGR_FMPI2C1_SCL_Msk
12483#define SYSCFG_CFGR_FMPI2C1_SDA_Pos (1U)
12484#define SYSCFG_CFGR_FMPI2C1_SDA_Msk (0x1UL << SYSCFG_CFGR_FMPI2C1_SDA_Pos)
12485#define SYSCFG_CFGR_FMPI2C1_SDA SYSCFG_CFGR_FMPI2C1_SDA_Msk
12486
12487/****************** Bit definition for SYSCFG_CFGR2 register *****************/
12488#define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
12489#define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1UL << SYSCFG_CFGR2_LOCKUP_LOCK_Pos)
12490#define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk
12491#define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
12492#define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1UL << SYSCFG_CFGR2_PVD_LOCK_Pos)
12493#define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk
12494/****************** Bit definition for SYSCFG_MCHDLYCR register *****************/
12495#define SYSCFG_MCHDLYCR_BSCKSEL_Pos (0U)
12496#define SYSCFG_MCHDLYCR_BSCKSEL_Msk (0x1UL << SYSCFG_MCHDLYCR_BSCKSEL_Pos)
12497#define SYSCFG_MCHDLYCR_BSCKSEL SYSCFG_MCHDLYCR_BSCKSEL_Msk
12498#define SYSCFG_MCHDLYCR_MCHDLY1EN_Pos (1U)
12499#define SYSCFG_MCHDLYCR_MCHDLY1EN_Msk (0x1UL << SYSCFG_MCHDLYCR_MCHDLY1EN_Pos)
12500#define SYSCFG_MCHDLYCR_MCHDLY1EN SYSCFG_MCHDLYCR_MCHDLY1EN_Msk
12501#define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos (2U)
12502#define SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1D0SEL_Pos)
12503#define SYSCFG_MCHDLYCR_DFSDM1D0SEL SYSCFG_MCHDLYCR_DFSDM1D0SEL_Msk
12504#define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos (3U)
12505#define SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1D2SEL_Pos)
12506#define SYSCFG_MCHDLYCR_DFSDM1D2SEL SYSCFG_MCHDLYCR_DFSDM1D2SEL_Msk
12507#define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos (4U)
12508#define SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Pos)
12509#define SYSCFG_MCHDLYCR_DFSDM1CK02SEL SYSCFG_MCHDLYCR_DFSDM1CK02SEL_Msk
12510#define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos (5U)
12511#define SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Pos)
12512#define SYSCFG_MCHDLYCR_DFSDM1CK13SEL SYSCFG_MCHDLYCR_DFSDM1CK13SEL_Msk
12513#define SYSCFG_MCHDLYCR_DFSDM1CFG_Pos (6U)
12514#define SYSCFG_MCHDLYCR_DFSDM1CFG_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CFG_Pos)
12515#define SYSCFG_MCHDLYCR_DFSDM1CFG SYSCFG_MCHDLYCR_DFSDM1CFG_Msk
12516#define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos (7U)
12517#define SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Pos)
12518#define SYSCFG_MCHDLYCR_DFSDM1CKOSEL SYSCFG_MCHDLYCR_DFSDM1CKOSEL_Msk
12519#define SYSCFG_MCHDLYCR_MCHDLY2EN_Pos (8U)
12520#define SYSCFG_MCHDLYCR_MCHDLY2EN_Msk (0x1UL << SYSCFG_MCHDLYCR_MCHDLY2EN_Pos)
12521#define SYSCFG_MCHDLYCR_MCHDLY2EN SYSCFG_MCHDLYCR_MCHDLY2EN_Msk
12522#define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos (9U)
12523#define SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D0SEL_Pos)
12524#define SYSCFG_MCHDLYCR_DFSDM2D0SEL SYSCFG_MCHDLYCR_DFSDM2D0SEL_Msk
12525#define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos (10U)
12526#define SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D2SEL_Pos)
12527#define SYSCFG_MCHDLYCR_DFSDM2D2SEL SYSCFG_MCHDLYCR_DFSDM2D2SEL_Msk
12528#define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos (11U)
12529#define SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D4SEL_Pos)
12530#define SYSCFG_MCHDLYCR_DFSDM2D4SEL SYSCFG_MCHDLYCR_DFSDM2D4SEL_Msk
12531#define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos (12U)
12532#define SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2D6SEL_Pos)
12533#define SYSCFG_MCHDLYCR_DFSDM2D6SEL SYSCFG_MCHDLYCR_DFSDM2D6SEL_Msk
12534#define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos (13U)
12535#define SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Pos)
12536#define SYSCFG_MCHDLYCR_DFSDM2CK04SEL SYSCFG_MCHDLYCR_DFSDM2CK04SEL_Msk
12537#define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos (14U)
12538#define SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Pos)
12539#define SYSCFG_MCHDLYCR_DFSDM2CK15SEL SYSCFG_MCHDLYCR_DFSDM2CK15SEL_Msk
12540#define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos (15U)
12541#define SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Pos)
12542#define SYSCFG_MCHDLYCR_DFSDM2CK26SEL SYSCFG_MCHDLYCR_DFSDM2CK26SEL_Msk
12543#define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos (16U)
12544#define SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Pos)
12545#define SYSCFG_MCHDLYCR_DFSDM2CK37SEL SYSCFG_MCHDLYCR_DFSDM2CK37SEL_Msk
12546#define SYSCFG_MCHDLYCR_DFSDM2CFG_Pos (17U)
12547#define SYSCFG_MCHDLYCR_DFSDM2CFG_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CFG_Pos)
12548#define SYSCFG_MCHDLYCR_DFSDM2CFG SYSCFG_MCHDLYCR_DFSDM2CFG_Msk
12549#define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos (18U)
12550#define SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk (0x1UL << SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Pos)
12551#define SYSCFG_MCHDLYCR_DFSDM2CKOSEL SYSCFG_MCHDLYCR_DFSDM2CKOSEL_Msk
12552
12553/******************************************************************************/
12554/* */
12555/* TIM */
12556/* */
12557/******************************************************************************/
12558/******************* Bit definition for TIM_CR1 register ********************/
12559#define TIM_CR1_CEN_Pos (0U)
12560#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
12561#define TIM_CR1_CEN TIM_CR1_CEN_Msk
12562#define TIM_CR1_UDIS_Pos (1U)
12563#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
12564#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
12565#define TIM_CR1_URS_Pos (2U)
12566#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
12567#define TIM_CR1_URS TIM_CR1_URS_Msk
12568#define TIM_CR1_OPM_Pos (3U)
12569#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
12570#define TIM_CR1_OPM TIM_CR1_OPM_Msk
12571#define TIM_CR1_DIR_Pos (4U)
12572#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
12573#define TIM_CR1_DIR TIM_CR1_DIR_Msk
12574
12575#define TIM_CR1_CMS_Pos (5U)
12576#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
12577#define TIM_CR1_CMS TIM_CR1_CMS_Msk
12578#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
12579#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
12580
12581#define TIM_CR1_ARPE_Pos (7U)
12582#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
12583#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
12584
12585#define TIM_CR1_CKD_Pos (8U)
12586#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
12587#define TIM_CR1_CKD TIM_CR1_CKD_Msk
12588#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
12589#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
12590
12591/******************* Bit definition for TIM_CR2 register ********************/
12592#define TIM_CR2_CCPC_Pos (0U)
12593#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
12594#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
12595#define TIM_CR2_CCUS_Pos (2U)
12596#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
12597#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
12598#define TIM_CR2_CCDS_Pos (3U)
12599#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
12600#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
12601
12602#define TIM_CR2_MMS_Pos (4U)
12603#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
12604#define TIM_CR2_MMS TIM_CR2_MMS_Msk
12605#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
12606#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
12607#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
12608
12609#define TIM_CR2_TI1S_Pos (7U)
12610#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
12611#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
12612#define TIM_CR2_OIS1_Pos (8U)
12613#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
12614#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
12615#define TIM_CR2_OIS1N_Pos (9U)
12616#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
12617#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
12618#define TIM_CR2_OIS2_Pos (10U)
12619#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
12620#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
12621#define TIM_CR2_OIS2N_Pos (11U)
12622#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
12623#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
12624#define TIM_CR2_OIS3_Pos (12U)
12625#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
12626#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
12627#define TIM_CR2_OIS3N_Pos (13U)
12628#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
12629#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
12630#define TIM_CR2_OIS4_Pos (14U)
12631#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
12632#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
12633
12634/******************* Bit definition for TIM_SMCR register *******************/
12635#define TIM_SMCR_SMS_Pos (0U)
12636#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
12637#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
12638#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
12639#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
12640#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
12641
12642#define TIM_SMCR_TS_Pos (4U)
12643#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
12644#define TIM_SMCR_TS TIM_SMCR_TS_Msk
12645#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
12646#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
12647#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
12648
12649#define TIM_SMCR_MSM_Pos (7U)
12650#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
12651#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
12652
12653#define TIM_SMCR_ETF_Pos (8U)
12654#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
12655#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
12656#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
12657#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
12658#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
12659#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
12660
12661#define TIM_SMCR_ETPS_Pos (12U)
12662#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
12663#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
12664#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
12665#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
12666
12667#define TIM_SMCR_ECE_Pos (14U)
12668#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
12669#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
12670#define TIM_SMCR_ETP_Pos (15U)
12671#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
12672#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
12673
12674/******************* Bit definition for TIM_DIER register *******************/
12675#define TIM_DIER_UIE_Pos (0U)
12676#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
12677#define TIM_DIER_UIE TIM_DIER_UIE_Msk
12678#define TIM_DIER_CC1IE_Pos (1U)
12679#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
12680#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
12681#define TIM_DIER_CC2IE_Pos (2U)
12682#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
12683#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
12684#define TIM_DIER_CC3IE_Pos (3U)
12685#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
12686#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
12687#define TIM_DIER_CC4IE_Pos (4U)
12688#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
12689#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
12690#define TIM_DIER_COMIE_Pos (5U)
12691#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
12692#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
12693#define TIM_DIER_TIE_Pos (6U)
12694#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
12695#define TIM_DIER_TIE TIM_DIER_TIE_Msk
12696#define TIM_DIER_BIE_Pos (7U)
12697#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
12698#define TIM_DIER_BIE TIM_DIER_BIE_Msk
12699#define TIM_DIER_UDE_Pos (8U)
12700#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
12701#define TIM_DIER_UDE TIM_DIER_UDE_Msk
12702#define TIM_DIER_CC1DE_Pos (9U)
12703#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
12704#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
12705#define TIM_DIER_CC2DE_Pos (10U)
12706#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
12707#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
12708#define TIM_DIER_CC3DE_Pos (11U)
12709#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
12710#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
12711#define TIM_DIER_CC4DE_Pos (12U)
12712#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
12713#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
12714#define TIM_DIER_COMDE_Pos (13U)
12715#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
12716#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
12717#define TIM_DIER_TDE_Pos (14U)
12718#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
12719#define TIM_DIER_TDE TIM_DIER_TDE_Msk
12720
12721/******************** Bit definition for TIM_SR register ********************/
12722#define TIM_SR_UIF_Pos (0U)
12723#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
12724#define TIM_SR_UIF TIM_SR_UIF_Msk
12725#define TIM_SR_CC1IF_Pos (1U)
12726#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
12727#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
12728#define TIM_SR_CC2IF_Pos (2U)
12729#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
12730#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
12731#define TIM_SR_CC3IF_Pos (3U)
12732#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
12733#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
12734#define TIM_SR_CC4IF_Pos (4U)
12735#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
12736#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
12737#define TIM_SR_COMIF_Pos (5U)
12738#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
12739#define TIM_SR_COMIF TIM_SR_COMIF_Msk
12740#define TIM_SR_TIF_Pos (6U)
12741#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
12742#define TIM_SR_TIF TIM_SR_TIF_Msk
12743#define TIM_SR_BIF_Pos (7U)
12744#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
12745#define TIM_SR_BIF TIM_SR_BIF_Msk
12746#define TIM_SR_CC1OF_Pos (9U)
12747#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
12748#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
12749#define TIM_SR_CC2OF_Pos (10U)
12750#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
12751#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
12752#define TIM_SR_CC3OF_Pos (11U)
12753#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
12754#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
12755#define TIM_SR_CC4OF_Pos (12U)
12756#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
12757#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
12758
12759/******************* Bit definition for TIM_EGR register ********************/
12760#define TIM_EGR_UG_Pos (0U)
12761#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
12762#define TIM_EGR_UG TIM_EGR_UG_Msk
12763#define TIM_EGR_CC1G_Pos (1U)
12764#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
12765#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
12766#define TIM_EGR_CC2G_Pos (2U)
12767#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
12768#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
12769#define TIM_EGR_CC3G_Pos (3U)
12770#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
12771#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
12772#define TIM_EGR_CC4G_Pos (4U)
12773#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
12774#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
12775#define TIM_EGR_COMG_Pos (5U)
12776#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
12777#define TIM_EGR_COMG TIM_EGR_COMG_Msk
12778#define TIM_EGR_TG_Pos (6U)
12779#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
12780#define TIM_EGR_TG TIM_EGR_TG_Msk
12781#define TIM_EGR_BG_Pos (7U)
12782#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
12783#define TIM_EGR_BG TIM_EGR_BG_Msk
12784
12785/****************** Bit definition for TIM_CCMR1 register *******************/
12786#define TIM_CCMR1_CC1S_Pos (0U)
12787#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
12788#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
12789#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
12790#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
12791
12792#define TIM_CCMR1_OC1FE_Pos (2U)
12793#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
12794#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
12795#define TIM_CCMR1_OC1PE_Pos (3U)
12796#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
12797#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
12798
12799#define TIM_CCMR1_OC1M_Pos (4U)
12800#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
12801#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
12802#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
12803#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
12804#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
12805
12806#define TIM_CCMR1_OC1CE_Pos (7U)
12807#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
12808#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
12809
12810#define TIM_CCMR1_CC2S_Pos (8U)
12811#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
12812#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
12813#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
12814#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
12815
12816#define TIM_CCMR1_OC2FE_Pos (10U)
12817#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
12818#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
12819#define TIM_CCMR1_OC2PE_Pos (11U)
12820#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
12821#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
12822
12823#define TIM_CCMR1_OC2M_Pos (12U)
12824#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
12825#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
12826#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
12827#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
12828#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
12829
12830#define TIM_CCMR1_OC2CE_Pos (15U)
12831#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
12832#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
12833
12834/*----------------------------------------------------------------------------*/
12835
12836#define TIM_CCMR1_IC1PSC_Pos (2U)
12837#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
12838#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
12839#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
12840#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
12841
12842#define TIM_CCMR1_IC1F_Pos (4U)
12843#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
12844#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
12845#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
12846#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
12847#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
12848#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
12849
12850#define TIM_CCMR1_IC2PSC_Pos (10U)
12851#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
12852#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
12853#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
12854#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
12855
12856#define TIM_CCMR1_IC2F_Pos (12U)
12857#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
12858#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
12859#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
12860#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
12861#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
12862#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
12863
12864/****************** Bit definition for TIM_CCMR2 register *******************/
12865#define TIM_CCMR2_CC3S_Pos (0U)
12866#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
12867#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
12868#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
12869#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
12870
12871#define TIM_CCMR2_OC3FE_Pos (2U)
12872#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
12873#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
12874#define TIM_CCMR2_OC3PE_Pos (3U)
12875#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
12876#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
12877
12878#define TIM_CCMR2_OC3M_Pos (4U)
12879#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
12880#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
12881#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
12882#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
12883#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
12884
12885#define TIM_CCMR2_OC3CE_Pos (7U)
12886#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
12887#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
12888
12889#define TIM_CCMR2_CC4S_Pos (8U)
12890#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
12891#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
12892#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
12893#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
12894
12895#define TIM_CCMR2_OC4FE_Pos (10U)
12896#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
12897#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
12898#define TIM_CCMR2_OC4PE_Pos (11U)
12899#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
12900#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
12901
12902#define TIM_CCMR2_OC4M_Pos (12U)
12903#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
12904#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
12905#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
12906#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
12907#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
12908
12909#define TIM_CCMR2_OC4CE_Pos (15U)
12910#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
12911#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
12912
12913/*----------------------------------------------------------------------------*/
12914
12915#define TIM_CCMR2_IC3PSC_Pos (2U)
12916#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
12917#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
12918#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
12919#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
12920
12921#define TIM_CCMR2_IC3F_Pos (4U)
12922#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
12923#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
12924#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
12925#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
12926#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
12927#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
12928
12929#define TIM_CCMR2_IC4PSC_Pos (10U)
12930#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
12931#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
12932#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
12933#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
12934
12935#define TIM_CCMR2_IC4F_Pos (12U)
12936#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
12937#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
12938#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
12939#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
12940#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
12941#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
12942
12943/******************* Bit definition for TIM_CCER register *******************/
12944#define TIM_CCER_CC1E_Pos (0U)
12945#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
12946#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
12947#define TIM_CCER_CC1P_Pos (1U)
12948#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
12949#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
12950#define TIM_CCER_CC1NE_Pos (2U)
12951#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
12952#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
12953#define TIM_CCER_CC1NP_Pos (3U)
12954#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
12955#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
12956#define TIM_CCER_CC2E_Pos (4U)
12957#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
12958#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
12959#define TIM_CCER_CC2P_Pos (5U)
12960#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
12961#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
12962#define TIM_CCER_CC2NE_Pos (6U)
12963#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
12964#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
12965#define TIM_CCER_CC2NP_Pos (7U)
12966#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
12967#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
12968#define TIM_CCER_CC3E_Pos (8U)
12969#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
12970#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
12971#define TIM_CCER_CC3P_Pos (9U)
12972#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
12973#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
12974#define TIM_CCER_CC3NE_Pos (10U)
12975#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
12976#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
12977#define TIM_CCER_CC3NP_Pos (11U)
12978#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
12979#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
12980#define TIM_CCER_CC4E_Pos (12U)
12981#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
12982#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
12983#define TIM_CCER_CC4P_Pos (13U)
12984#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
12985#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
12986#define TIM_CCER_CC4NP_Pos (15U)
12987#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
12988#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
12989
12990/******************* Bit definition for TIM_CNT register ********************/
12991#define TIM_CNT_CNT_Pos (0U)
12992#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
12993#define TIM_CNT_CNT TIM_CNT_CNT_Msk
12994
12995/******************* Bit definition for TIM_PSC register ********************/
12996#define TIM_PSC_PSC_Pos (0U)
12997#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
12998#define TIM_PSC_PSC TIM_PSC_PSC_Msk
12999
13000/******************* Bit definition for TIM_ARR register ********************/
13001#define TIM_ARR_ARR_Pos (0U)
13002#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
13003#define TIM_ARR_ARR TIM_ARR_ARR_Msk
13004
13005/******************* Bit definition for TIM_RCR register ********************/
13006#define TIM_RCR_REP_Pos (0U)
13007#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
13008#define TIM_RCR_REP TIM_RCR_REP_Msk
13009
13010/******************* Bit definition for TIM_CCR1 register *******************/
13011#define TIM_CCR1_CCR1_Pos (0U)
13012#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
13013#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
13014
13015/******************* Bit definition for TIM_CCR2 register *******************/
13016#define TIM_CCR2_CCR2_Pos (0U)
13017#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
13018#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
13019
13020/******************* Bit definition for TIM_CCR3 register *******************/
13021#define TIM_CCR3_CCR3_Pos (0U)
13022#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
13023#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
13024
13025/******************* Bit definition for TIM_CCR4 register *******************/
13026#define TIM_CCR4_CCR4_Pos (0U)
13027#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
13028#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
13029
13030/******************* Bit definition for TIM_BDTR register *******************/
13031#define TIM_BDTR_DTG_Pos (0U)
13032#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
13033#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
13034#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
13035#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
13036#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
13037#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
13038#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
13039#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
13040#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
13041#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
13042
13043#define TIM_BDTR_LOCK_Pos (8U)
13044#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
13045#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
13046#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
13047#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
13048
13049#define TIM_BDTR_OSSI_Pos (10U)
13050#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
13051#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
13052#define TIM_BDTR_OSSR_Pos (11U)
13053#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
13054#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
13055#define TIM_BDTR_BKE_Pos (12U)
13056#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
13057#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
13058#define TIM_BDTR_BKP_Pos (13U)
13059#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
13060#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
13061#define TIM_BDTR_AOE_Pos (14U)
13062#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
13063#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
13064#define TIM_BDTR_MOE_Pos (15U)
13065#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
13066#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
13067
13068/******************* Bit definition for TIM_DCR register ********************/
13069#define TIM_DCR_DBA_Pos (0U)
13070#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
13071#define TIM_DCR_DBA TIM_DCR_DBA_Msk
13072#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
13073#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
13074#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
13075#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
13076#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
13077
13078#define TIM_DCR_DBL_Pos (8U)
13079#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
13080#define TIM_DCR_DBL TIM_DCR_DBL_Msk
13081#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
13082#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
13083#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
13084#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
13085#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
13086
13087/******************* Bit definition for TIM_DMAR register *******************/
13088#define TIM_DMAR_DMAB_Pos (0U)
13089#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
13090#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
13091
13092/******************* Bit definition for TIM_OR register *********************/
13093#define TIM_OR_TI1_RMP_Pos (0U)
13094#define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)
13095#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk
13096#define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)
13097#define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)
13098
13099#define TIM_OR_TI4_RMP_Pos (6U)
13100#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
13101#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
13102#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
13103#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
13104#define TIM_OR_ITR1_RMP_Pos (10U)
13105#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
13106#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
13107#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
13108#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
13109
13110/******************************************************************************/
13111/* */
13112/* Low Power Timer (LPTIM) */
13113/* */
13114/******************************************************************************/
13115/****************** Bit definition for LPTIM_ISR register *******************/
13116#define LPTIM_ISR_CMPM_Pos (0U)
13117#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
13118#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
13119#define LPTIM_ISR_ARRM_Pos (1U)
13120#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
13121#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
13122#define LPTIM_ISR_EXTTRIG_Pos (2U)
13123#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
13124#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
13125#define LPTIM_ISR_CMPOK_Pos (3U)
13126#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
13127#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
13128#define LPTIM_ISR_ARROK_Pos (4U)
13129#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
13130#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
13131#define LPTIM_ISR_UP_Pos (5U)
13132#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
13133#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
13134#define LPTIM_ISR_DOWN_Pos (6U)
13135#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
13136#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
13137
13138/****************** Bit definition for LPTIM_ICR register *******************/
13139#define LPTIM_ICR_CMPMCF_Pos (0U)
13140#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
13141#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
13142#define LPTIM_ICR_ARRMCF_Pos (1U)
13143#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
13144#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
13145#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
13146#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
13147#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
13148#define LPTIM_ICR_CMPOKCF_Pos (3U)
13149#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
13150#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
13151#define LPTIM_ICR_ARROKCF_Pos (4U)
13152#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
13153#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
13154#define LPTIM_ICR_UPCF_Pos (5U)
13155#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
13156#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
13157#define LPTIM_ICR_DOWNCF_Pos (6U)
13158#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
13159#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
13160
13161/****************** Bit definition for LPTIM_IER register ********************/
13162#define LPTIM_IER_CMPMIE_Pos (0U)
13163#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
13164#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
13165#define LPTIM_IER_ARRMIE_Pos (1U)
13166#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
13167#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
13168#define LPTIM_IER_EXTTRIGIE_Pos (2U)
13169#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
13170#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
13171#define LPTIM_IER_CMPOKIE_Pos (3U)
13172#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
13173#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
13174#define LPTIM_IER_ARROKIE_Pos (4U)
13175#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
13176#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
13177#define LPTIM_IER_UPIE_Pos (5U)
13178#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
13179#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
13180#define LPTIM_IER_DOWNIE_Pos (6U)
13181#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
13182#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
13183
13184/****************** Bit definition for LPTIM_CFGR register *******************/
13185#define LPTIM_CFGR_CKSEL_Pos (0U)
13186#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
13187#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
13188
13189#define LPTIM_CFGR_CKPOL_Pos (1U)
13190#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
13191#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
13192#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
13193#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
13194
13195#define LPTIM_CFGR_CKFLT_Pos (3U)
13196#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
13197#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
13198#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
13199#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
13200
13201#define LPTIM_CFGR_TRGFLT_Pos (6U)
13202#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
13203#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
13204#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
13205#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
13206
13207#define LPTIM_CFGR_PRESC_Pos (9U)
13208#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
13209#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
13210#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
13211#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
13212#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
13213
13214#define LPTIM_CFGR_TRIGSEL_Pos (13U)
13215#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
13216#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
13217#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
13218#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
13219#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
13220
13221#define LPTIM_CFGR_TRIGEN_Pos (17U)
13222#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
13223#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
13224#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
13225#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
13226
13227#define LPTIM_CFGR_TIMOUT_Pos (19U)
13228#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
13229#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
13230#define LPTIM_CFGR_WAVE_Pos (20U)
13231#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
13232#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
13233#define LPTIM_CFGR_WAVPOL_Pos (21U)
13234#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
13235#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
13236#define LPTIM_CFGR_PRELOAD_Pos (22U)
13237#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
13238#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
13239#define LPTIM_CFGR_COUNTMODE_Pos (23U)
13240#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
13241#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
13242#define LPTIM_CFGR_ENC_Pos (24U)
13243#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
13244#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
13245
13246/****************** Bit definition for LPTIM_CR register ********************/
13247#define LPTIM_CR_ENABLE_Pos (0U)
13248#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
13249#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
13250#define LPTIM_CR_SNGSTRT_Pos (1U)
13251#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)
13252#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
13253#define LPTIM_CR_CNTSTRT_Pos (2U)
13254#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
13255#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
13256
13257/****************** Bit definition for LPTIM_CMP register *******************/
13258#define LPTIM_CMP_CMP_Pos (0U)
13259#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
13260#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
13261
13262/****************** Bit definition for LPTIM_ARR register *******************/
13263#define LPTIM_ARR_ARR_Pos (0U)
13264#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
13265#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
13266
13267/****************** Bit definition for LPTIM_CNT register *******************/
13268#define LPTIM_CNT_CNT_Pos (0U)
13269#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
13270#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
13271
13272/****************** Bit definition for LPTIM_OR register *******************/
13273#define LPTIM_OR_LPT_IN1_RMP_Pos (0U)
13274#define LPTIM_OR_LPT_IN1_RMP_Msk (0x3UL << LPTIM_OR_LPT_IN1_RMP_Pos)
13275#define LPTIM_OR_LPT_IN1_RMP LPTIM_OR_LPT_IN1_RMP_Msk
13276#define LPTIM_OR_LPT_IN1_RMP_0 (0x1UL << LPTIM_OR_LPT_IN1_RMP_Pos)
13277#define LPTIM_OR_LPT_IN1_RMP_1 (0x2UL << LPTIM_OR_LPT_IN1_RMP_Pos)
13278#define LPTIM_OR_TIM1_ITR2_RMP_Pos (2U)
13279#define LPTIM_OR_TIM1_ITR2_RMP_Msk (0x1UL << LPTIM_OR_TIM1_ITR2_RMP_Pos)
13280#define LPTIM_OR_TIM1_ITR2_RMP LPTIM_OR_TIM1_ITR2_RMP_Msk
13281#define LPTIM_OR_TIM5_ITR1_RMP_Pos (3U)
13282#define LPTIM_OR_TIM5_ITR1_RMP_Msk (0x1UL << LPTIM_OR_TIM5_ITR1_RMP_Pos)
13283#define LPTIM_OR_TIM5_ITR1_RMP LPTIM_OR_TIM5_ITR1_RMP_Msk
13284#define LPTIM_OR_TIM9_ITR1_RMP_Pos (4U)
13285#define LPTIM_OR_TIM9_ITR1_RMP_Msk (0x1UL << LPTIM_OR_TIM9_ITR1_RMP_Pos)
13286#define LPTIM_OR_TIM9_ITR1_RMP LPTIM_OR_TIM9_ITR1_RMP_Msk
13287
13288/* Legacy Defines */
13289#define LPTIM_OR_OR LPTIM_OR_LPT_IN1_RMP
13290#define LPTIM_OR_OR_0 LPTIM_OR_LPT_IN1_RMP_0
13291#define LPTIM_OR_OR_1 LPTIM_OR_LPT_IN1_RMP_1
13292
13293
13294/******************************************************************************/
13295/* */
13296/* Universal Synchronous Asynchronous Receiver Transmitter */
13297/* */
13298/******************************************************************************/
13299/******************* Bit definition for USART_SR register *******************/
13300#define USART_SR_PE_Pos (0U)
13301#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
13302#define USART_SR_PE USART_SR_PE_Msk
13303#define USART_SR_FE_Pos (1U)
13304#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
13305#define USART_SR_FE USART_SR_FE_Msk
13306#define USART_SR_NE_Pos (2U)
13307#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
13308#define USART_SR_NE USART_SR_NE_Msk
13309#define USART_SR_ORE_Pos (3U)
13310#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
13311#define USART_SR_ORE USART_SR_ORE_Msk
13312#define USART_SR_IDLE_Pos (4U)
13313#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
13314#define USART_SR_IDLE USART_SR_IDLE_Msk
13315#define USART_SR_RXNE_Pos (5U)
13316#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
13317#define USART_SR_RXNE USART_SR_RXNE_Msk
13318#define USART_SR_TC_Pos (6U)
13319#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
13320#define USART_SR_TC USART_SR_TC_Msk
13321#define USART_SR_TXE_Pos (7U)
13322#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
13323#define USART_SR_TXE USART_SR_TXE_Msk
13324#define USART_SR_LBD_Pos (8U)
13325#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
13326#define USART_SR_LBD USART_SR_LBD_Msk
13327#define USART_SR_CTS_Pos (9U)
13328#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
13329#define USART_SR_CTS USART_SR_CTS_Msk
13330
13331/******************* Bit definition for USART_DR register *******************/
13332#define USART_DR_DR_Pos (0U)
13333#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
13334#define USART_DR_DR USART_DR_DR_Msk
13335
13336/****************** Bit definition for USART_BRR register *******************/
13337#define USART_BRR_DIV_Fraction_Pos (0U)
13338#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
13339#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
13340#define USART_BRR_DIV_Mantissa_Pos (4U)
13341#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
13342#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
13343
13344/****************** Bit definition for USART_CR1 register *******************/
13345#define USART_CR1_SBK_Pos (0U)
13346#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
13347#define USART_CR1_SBK USART_CR1_SBK_Msk
13348#define USART_CR1_RWU_Pos (1U)
13349#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
13350#define USART_CR1_RWU USART_CR1_RWU_Msk
13351#define USART_CR1_RE_Pos (2U)
13352#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
13353#define USART_CR1_RE USART_CR1_RE_Msk
13354#define USART_CR1_TE_Pos (3U)
13355#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
13356#define USART_CR1_TE USART_CR1_TE_Msk
13357#define USART_CR1_IDLEIE_Pos (4U)
13358#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
13359#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
13360#define USART_CR1_RXNEIE_Pos (5U)
13361#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
13362#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
13363#define USART_CR1_TCIE_Pos (6U)
13364#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
13365#define USART_CR1_TCIE USART_CR1_TCIE_Msk
13366#define USART_CR1_TXEIE_Pos (7U)
13367#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
13368#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
13369#define USART_CR1_PEIE_Pos (8U)
13370#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
13371#define USART_CR1_PEIE USART_CR1_PEIE_Msk
13372#define USART_CR1_PS_Pos (9U)
13373#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
13374#define USART_CR1_PS USART_CR1_PS_Msk
13375#define USART_CR1_PCE_Pos (10U)
13376#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
13377#define USART_CR1_PCE USART_CR1_PCE_Msk
13378#define USART_CR1_WAKE_Pos (11U)
13379#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
13380#define USART_CR1_WAKE USART_CR1_WAKE_Msk
13381#define USART_CR1_M_Pos (12U)
13382#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
13383#define USART_CR1_M USART_CR1_M_Msk
13384#define USART_CR1_UE_Pos (13U)
13385#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
13386#define USART_CR1_UE USART_CR1_UE_Msk
13387#define USART_CR1_OVER8_Pos (15U)
13388#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
13389#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
13390
13391/****************** Bit definition for USART_CR2 register *******************/
13392#define USART_CR2_ADD_Pos (0U)
13393#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
13394#define USART_CR2_ADD USART_CR2_ADD_Msk
13395#define USART_CR2_LBDL_Pos (5U)
13396#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
13397#define USART_CR2_LBDL USART_CR2_LBDL_Msk
13398#define USART_CR2_LBDIE_Pos (6U)
13399#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
13400#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
13401#define USART_CR2_LBCL_Pos (8U)
13402#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
13403#define USART_CR2_LBCL USART_CR2_LBCL_Msk
13404#define USART_CR2_CPHA_Pos (9U)
13405#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
13406#define USART_CR2_CPHA USART_CR2_CPHA_Msk
13407#define USART_CR2_CPOL_Pos (10U)
13408#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
13409#define USART_CR2_CPOL USART_CR2_CPOL_Msk
13410#define USART_CR2_CLKEN_Pos (11U)
13411#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
13412#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
13413
13414#define USART_CR2_STOP_Pos (12U)
13415#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
13416#define USART_CR2_STOP USART_CR2_STOP_Msk
13417#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
13418#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
13419
13420#define USART_CR2_LINEN_Pos (14U)
13421#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
13422#define USART_CR2_LINEN USART_CR2_LINEN_Msk
13423
13424/****************** Bit definition for USART_CR3 register *******************/
13425#define USART_CR3_EIE_Pos (0U)
13426#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
13427#define USART_CR3_EIE USART_CR3_EIE_Msk
13428#define USART_CR3_IREN_Pos (1U)
13429#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
13430#define USART_CR3_IREN USART_CR3_IREN_Msk
13431#define USART_CR3_IRLP_Pos (2U)
13432#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
13433#define USART_CR3_IRLP USART_CR3_IRLP_Msk
13434#define USART_CR3_HDSEL_Pos (3U)
13435#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
13436#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
13437#define USART_CR3_NACK_Pos (4U)
13438#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
13439#define USART_CR3_NACK USART_CR3_NACK_Msk
13440#define USART_CR3_SCEN_Pos (5U)
13441#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
13442#define USART_CR3_SCEN USART_CR3_SCEN_Msk
13443#define USART_CR3_DMAR_Pos (6U)
13444#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
13445#define USART_CR3_DMAR USART_CR3_DMAR_Msk
13446#define USART_CR3_DMAT_Pos (7U)
13447#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
13448#define USART_CR3_DMAT USART_CR3_DMAT_Msk
13449#define USART_CR3_RTSE_Pos (8U)
13450#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
13451#define USART_CR3_RTSE USART_CR3_RTSE_Msk
13452#define USART_CR3_CTSE_Pos (9U)
13453#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
13454#define USART_CR3_CTSE USART_CR3_CTSE_Msk
13455#define USART_CR3_CTSIE_Pos (10U)
13456#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
13457#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
13458#define USART_CR3_ONEBIT_Pos (11U)
13459#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
13460#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
13461
13462/****************** Bit definition for USART_GTPR register ******************/
13463#define USART_GTPR_PSC_Pos (0U)
13464#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
13465#define USART_GTPR_PSC USART_GTPR_PSC_Msk
13466#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
13467#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
13468#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
13469#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
13470#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
13471#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
13472#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
13473#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
13474
13475#define USART_GTPR_GT_Pos (8U)
13476#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
13477#define USART_GTPR_GT USART_GTPR_GT_Msk
13478
13479/******************************************************************************/
13480/* */
13481/* Window WATCHDOG */
13482/* */
13483/******************************************************************************/
13484/******************* Bit definition for WWDG_CR register ********************/
13485#define WWDG_CR_T_Pos (0U)
13486#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
13487#define WWDG_CR_T WWDG_CR_T_Msk
13488#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
13489#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
13490#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
13491#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
13492#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
13493#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
13494#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
13495/* Legacy defines */
13496#define WWDG_CR_T0 WWDG_CR_T_0
13497#define WWDG_CR_T1 WWDG_CR_T_1
13498#define WWDG_CR_T2 WWDG_CR_T_2
13499#define WWDG_CR_T3 WWDG_CR_T_3
13500#define WWDG_CR_T4 WWDG_CR_T_4
13501#define WWDG_CR_T5 WWDG_CR_T_5
13502#define WWDG_CR_T6 WWDG_CR_T_6
13503
13504#define WWDG_CR_WDGA_Pos (7U)
13505#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
13506#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
13507
13508/******************* Bit definition for WWDG_CFR register *******************/
13509#define WWDG_CFR_W_Pos (0U)
13510#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
13511#define WWDG_CFR_W WWDG_CFR_W_Msk
13512#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
13513#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
13514#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
13515#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
13516#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
13517#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
13518#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
13519/* Legacy defines */
13520#define WWDG_CFR_W0 WWDG_CFR_W_0
13521#define WWDG_CFR_W1 WWDG_CFR_W_1
13522#define WWDG_CFR_W2 WWDG_CFR_W_2
13523#define WWDG_CFR_W3 WWDG_CFR_W_3
13524#define WWDG_CFR_W4 WWDG_CFR_W_4
13525#define WWDG_CFR_W5 WWDG_CFR_W_5
13526#define WWDG_CFR_W6 WWDG_CFR_W_6
13527
13528#define WWDG_CFR_WDGTB_Pos (7U)
13529#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
13530#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
13531#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
13532#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
13533/* Legacy defines */
13534#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
13535#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
13536
13537#define WWDG_CFR_EWI_Pos (9U)
13538#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
13539#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
13540
13541/******************* Bit definition for WWDG_SR register ********************/
13542#define WWDG_SR_EWIF_Pos (0U)
13543#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
13544#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
13545
13546
13547/******************************************************************************/
13548/* */
13549/* DBG */
13550/* */
13551/******************************************************************************/
13552/******************** Bit definition for DBGMCU_IDCODE register *************/
13553#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
13554#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
13555#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
13556#define DBGMCU_IDCODE_REV_ID_Pos (16U)
13557#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
13558#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
13559
13560/******************** Bit definition for DBGMCU_CR register *****************/
13561#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
13562#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
13563#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
13564#define DBGMCU_CR_DBG_STOP_Pos (1U)
13565#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
13566#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
13567#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
13568#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
13569#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
13570#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
13571#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
13572#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
13573
13574#define DBGMCU_CR_TRACE_MODE_Pos (6U)
13575#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
13576#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
13577#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
13578#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
13579
13580/******************** Bit definition for DBGMCU_APB1_FZ register ************/
13581#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
13582#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
13583#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
13584#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
13585#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
13586#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
13587#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
13588#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
13589#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
13590#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
13591#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
13592#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
13593#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
13594#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
13595#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
13596#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
13597#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
13598#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
13599#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
13600#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
13601#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
13602#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
13603#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
13604#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
13605#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
13606#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
13607#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
13608#define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos (9U)
13609#define DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Pos)
13610#define DBGMCU_APB1_FZ_DBG_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP_Msk
13611#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
13612#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
13613#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
13614#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
13615#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
13616#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
13617#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
13618#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
13619#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
13620#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
13621#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
13622#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
13623#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
13624#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
13625#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
13626#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
13627#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
13628#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
13629#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
13630#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos)
13631#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
13632#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
13633#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
13634#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
13635#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
13636#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
13637#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
13638#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos (27U)
13639#define DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN3_STOP_Pos)
13640#define DBGMCU_APB1_FZ_DBG_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP_Msk
13641
13642/******************** Bit definition for DBGMCU_APB2_FZ register ************/
13643#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
13644#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
13645#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
13646#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
13647#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
13648#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
13649#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
13650#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
13651#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
13652#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
13653#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
13654#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
13655#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
13656#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
13657#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
13658
13659/******************************************************************************/
13660/* */
13661/* USB_OTG */
13662/* */
13663/******************************************************************************/
13664/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
13665#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
13666#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
13667#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
13668#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
13669#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
13670#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
13671#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
13672#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
13673#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
13674#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
13675#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
13676#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
13677#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
13678#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
13679#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
13680#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
13681#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
13682#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
13683#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
13684#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
13685#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
13686#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
13687#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
13688#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
13689#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
13690#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
13691#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
13692#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
13693#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
13694#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
13695#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
13696#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
13697#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
13698#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
13699#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
13700#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
13701#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
13702#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
13703#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
13704#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
13705#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
13706#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
13707#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
13708#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
13709#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
13710#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
13711#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
13712#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
13713#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
13714#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
13715#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
13716#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
13717#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
13718#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
13719
13720/******************** Bit definition forUSB_OTG_HCFG register ********************/
13721
13722#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
13723#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
13724#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
13725#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
13726#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
13727#define USB_OTG_HCFG_FSLSS_Pos (2U)
13728#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
13729#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
13730
13731/******************** Bit definition for USB_OTG_DCFG register ********************/
13732
13733#define USB_OTG_DCFG_DSPD_Pos (0U)
13734#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
13735#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
13736#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
13737#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
13738#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
13739#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
13740#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
13741
13742#define USB_OTG_DCFG_DAD_Pos (4U)
13743#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
13744#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
13745#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
13746#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
13747#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
13748#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
13749#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
13750#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
13751#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
13752
13753#define USB_OTG_DCFG_PFIVL_Pos (11U)
13754#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
13755#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
13756#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
13757#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
13758
13759#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
13760#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
13761#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
13762
13763#define USB_OTG_DCFG_ERRATIM_Pos (15U)
13764#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
13765#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
13766
13767#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
13768#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13769#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
13770#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13771#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13772
13773/******************** Bit definition for USB_OTG_PCGCR register ********************/
13774#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
13775#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
13776#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
13777#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
13778#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
13779#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
13780#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
13781#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
13782#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
13783
13784/******************** Bit definition for USB_OTG_GOTGINT register ********************/
13785#define USB_OTG_GOTGINT_SEDET_Pos (2U)
13786#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
13787#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
13788#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
13789#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
13790#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
13791#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
13792#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
13793#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
13794#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
13795#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
13796#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
13797#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
13798#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
13799#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
13800#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
13801#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
13802#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
13803#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
13804#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos)
13805#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk
13806
13807/******************** Bit definition for USB_OTG_DCTL register ********************/
13808#define USB_OTG_DCTL_RWUSIG_Pos (0U)
13809#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
13810#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
13811#define USB_OTG_DCTL_SDIS_Pos (1U)
13812#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
13813#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
13814#define USB_OTG_DCTL_GINSTS_Pos (2U)
13815#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
13816#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
13817#define USB_OTG_DCTL_GONSTS_Pos (3U)
13818#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
13819#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
13820
13821#define USB_OTG_DCTL_TCTL_Pos (4U)
13822#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
13823#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
13824#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
13825#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
13826#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
13827#define USB_OTG_DCTL_SGINAK_Pos (7U)
13828#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
13829#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
13830#define USB_OTG_DCTL_CGINAK_Pos (8U)
13831#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
13832#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
13833#define USB_OTG_DCTL_SGONAK_Pos (9U)
13834#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
13835#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
13836#define USB_OTG_DCTL_CGONAK_Pos (10U)
13837#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
13838#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
13839#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
13840#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
13841#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
13842
13843/******************** Bit definition for USB_OTG_HFIR register ********************/
13844#define USB_OTG_HFIR_FRIVL_Pos (0U)
13845#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
13846#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
13847
13848/******************** Bit definition for USB_OTG_HFNUM register ********************/
13849#define USB_OTG_HFNUM_FRNUM_Pos (0U)
13850#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
13851#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
13852#define USB_OTG_HFNUM_FTREM_Pos (16U)
13853#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
13854#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
13855
13856/******************** Bit definition for USB_OTG_DSTS register ********************/
13857#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
13858#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
13859#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
13860
13861#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
13862#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
13863#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
13864#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
13865#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
13866#define USB_OTG_DSTS_EERR_Pos (3U)
13867#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
13868#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
13869#define USB_OTG_DSTS_FNSOF_Pos (8U)
13870#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
13871#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
13872
13873/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
13874#define USB_OTG_GAHBCFG_GINT_Pos (0U)
13875#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
13876#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
13877#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
13878#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13879#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
13880#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13881#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13882#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13883#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13884#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13885#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
13886#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
13887#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
13888#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
13889#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
13890#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
13891#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
13892#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
13893#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
13894
13895/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
13896
13897#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
13898#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13899#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
13900#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13901#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13902#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13903#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
13904#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
13905#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
13906#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
13907#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
13908#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
13909#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
13910#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
13911#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
13912#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
13913#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
13914#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
13915#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
13916#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
13917#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
13918#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
13919#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
13920#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
13921#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
13922#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
13923#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
13924#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
13925#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
13926#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
13927#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
13928#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
13929#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
13930#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
13931#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
13932#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
13933#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
13934#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
13935#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
13936#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
13937#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
13938#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
13939#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
13940#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
13941#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
13942#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
13943#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
13944#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
13945#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
13946#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
13947#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
13948#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
13949#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
13950#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
13951#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
13952#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
13953#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
13954#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
13955#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
13956#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
13957#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
13958
13959/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
13960#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
13961#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
13962#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
13963#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
13964#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
13965#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
13966#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
13967#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
13968#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
13969#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
13970#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
13971#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
13972#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
13973#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
13974#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
13975
13976
13977#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
13978#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13979#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
13980#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13981#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13982#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13983#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13984#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13985#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
13986#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
13987#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
13988#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
13989#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
13990#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
13991
13992/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
13993#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
13994#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
13995#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
13996#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
13997#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
13998#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
13999#define USB_OTG_DIEPMSK_TOM_Pos (3U)
14000#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
14001#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
14002#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
14003#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
14004#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
14005#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
14006#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
14007#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
14008#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
14009#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
14010#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
14011#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
14012#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
14013#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
14014#define USB_OTG_DIEPMSK_NAKM_Pos (13U)
14015#define USB_OTG_DIEPMSK_NAKM_Msk (0x1UL << USB_OTG_DIEPMSK_NAKM_Pos)
14016#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk
14017
14018/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
14019#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
14020#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
14021#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
14022#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
14023#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14024#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
14025#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14026#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14027#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14028#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14029#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14030#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14031#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14032#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
14033
14034#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
14035#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14036#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
14037#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14038#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14039#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14040#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14041#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14042#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14043#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14044#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
14045
14046/******************** Bit definition for USB_OTG_HAINT register ********************/
14047#define USB_OTG_HAINT_HAINT_Pos (0U)
14048#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
14049#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
14050
14051/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
14052#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
14053#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
14054#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
14055#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
14056#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
14057#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
14058#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
14059#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
14060#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
14061#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
14062#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
14063#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
14064#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
14065#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
14066#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
14067#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
14068#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
14069#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
14070#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
14071#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
14072#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
14073#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
14074#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
14075#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
14076#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
14077#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
14078#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
14079#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
14080#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
14081#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
14082#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
14083#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
14084#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
14085#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
14086#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
14087#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
14088/******************** Bit definition for USB_OTG_GINTSTS register ********************/
14089#define USB_OTG_GINTSTS_CMOD_Pos (0U)
14090#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
14091#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
14092#define USB_OTG_GINTSTS_MMIS_Pos (1U)
14093#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
14094#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
14095#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
14096#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
14097#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
14098#define USB_OTG_GINTSTS_SOF_Pos (3U)
14099#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
14100#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
14101#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
14102#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
14103#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
14104#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
14105#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
14106#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
14107#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
14108#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
14109#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
14110#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
14111#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
14112#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
14113#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
14114#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
14115#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
14116#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
14117#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
14118#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
14119#define USB_OTG_GINTSTS_USBRST_Pos (12U)
14120#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
14121#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
14122#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
14123#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
14124#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
14125#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
14126#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
14127#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
14128#define USB_OTG_GINTSTS_EOPF_Pos (15U)
14129#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
14130#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
14131#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
14132#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
14133#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
14134#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
14135#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
14136#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
14137#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
14138#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
14139#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
14140#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
14141#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
14142#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
14143#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
14144#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
14145#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
14146#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
14147#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
14148#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
14149#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
14150#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
14151#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
14152#define USB_OTG_GINTSTS_HCINT_Pos (25U)
14153#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
14154#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
14155#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
14156#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
14157#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
14158#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
14159#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
14160#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
14161#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
14162#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
14163#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
14164#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
14165#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
14166#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
14167#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
14168#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
14169#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
14170#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
14171#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
14172#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
14173
14174/******************** Bit definition for USB_OTG_GINTMSK register ********************/
14175#define USB_OTG_GINTMSK_MMISM_Pos (1U)
14176#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
14177#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
14178#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
14179#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
14180#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
14181#define USB_OTG_GINTMSK_SOFM_Pos (3U)
14182#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
14183#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
14184#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
14185#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
14186#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
14187#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
14188#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
14189#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
14190#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
14191#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
14192#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
14193#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
14194#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
14195#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
14196#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
14197#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
14198#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
14199#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
14200#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
14201#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
14202#define USB_OTG_GINTMSK_USBRST_Pos (12U)
14203#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
14204#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
14205#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
14206#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
14207#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
14208#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
14209#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
14210#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
14211#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
14212#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
14213#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
14214#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
14215#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
14216#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
14217#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
14218#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
14219#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
14220#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
14221#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
14222#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
14223#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
14224#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
14225#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
14226#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
14227#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
14228#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
14229#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
14230#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
14231#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
14232#define USB_OTG_GINTMSK_RSTDETM_Pos (23U)
14233#define USB_OTG_GINTMSK_RSTDETM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDETM_Pos)
14234#define USB_OTG_GINTMSK_RSTDETM USB_OTG_GINTMSK_RSTDETM_Msk
14235#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
14236#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
14237#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
14238#define USB_OTG_GINTMSK_HCIM_Pos (25U)
14239#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
14240#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
14241#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
14242#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
14243#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
14244#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
14245#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
14246#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
14247#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
14248#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
14249#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
14250#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
14251#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
14252#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
14253#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
14254#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
14255#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
14256#define USB_OTG_GINTMSK_WUIM_Pos (31U)
14257#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
14258#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
14259
14260/******************** Bit definition for USB_OTG_DAINT register ********************/
14261#define USB_OTG_DAINT_IEPINT_Pos (0U)
14262#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
14263#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
14264#define USB_OTG_DAINT_OEPINT_Pos (16U)
14265#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
14266#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
14267
14268/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
14269#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
14270#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
14271#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
14272
14273/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
14274#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
14275#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
14276#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
14277#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
14278#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
14279#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
14280#define USB_OTG_GRXSTSP_DPID_Pos (15U)
14281#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
14282#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
14283#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
14284#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
14285#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
14286
14287/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
14288#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
14289#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
14290#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
14291#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
14292#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
14293#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
14294
14295/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
14296#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
14297#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
14298#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
14299
14300/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
14301#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
14302#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
14303#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
14304
14305/******************** Bit definition for OTG register ********************/
14306#define USB_OTG_NPTXFSA_Pos (0U)
14307#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
14308#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
14309#define USB_OTG_NPTXFD_Pos (16U)
14310#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
14311#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
14312#define USB_OTG_TX0FSA_Pos (0U)
14313#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
14314#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
14315#define USB_OTG_TX0FD_Pos (16U)
14316#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
14317#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
14318
14319/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
14320#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
14321#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
14322#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
14323
14324/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
14325#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
14326#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
14327#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
14328
14329#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
14330#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14331#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
14332#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14333#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14334#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14335#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14336#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14337#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14338#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14339#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14340
14341#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
14342#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14343#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
14344#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14345#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14346#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14347#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14348#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14349#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14350#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14351
14352/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
14353#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
14354#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
14355#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
14356#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
14357#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
14358#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
14359
14360#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
14361#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14362#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
14363#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14364#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14365#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14366#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14367#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14368#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14369#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14370#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14371#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14372#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
14373#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
14374#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
14375
14376#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
14377#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14378#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
14379#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14380#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14381#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14382#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14383#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14384#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14385#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14386#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14387#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14388#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
14389#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
14390#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
14391
14392/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
14393#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
14394#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
14395#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
14396
14397/******************** Bit definition for USB_OTG_DEACHINT register ********************/
14398#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
14399#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
14400#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
14401#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
14402#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
14403#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
14404
14405/******************** Bit definition for USB_OTG_GCCFG register ********************/
14406#define USB_OTG_GCCFG_DCDET_Pos (0U)
14407#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos)
14408#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk
14409#define USB_OTG_GCCFG_PDET_Pos (1U)
14410#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos)
14411#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk
14412#define USB_OTG_GCCFG_SDET_Pos (2U)
14413#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos)
14414#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk
14415#define USB_OTG_GCCFG_PS2DET_Pos (3U)
14416#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos)
14417#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk
14418#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
14419#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
14420#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
14421#define USB_OTG_GCCFG_BCDEN_Pos (17U)
14422#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos)
14423#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk
14424#define USB_OTG_GCCFG_DCDEN_Pos (18U)
14425#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos)
14426#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk
14427#define USB_OTG_GCCFG_PDEN_Pos (19U)
14428#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos)
14429#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk
14430#define USB_OTG_GCCFG_SDEN_Pos (20U)
14431#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos)
14432#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk
14433#define USB_OTG_GCCFG_VBDEN_Pos (21U)
14434#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
14435#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
14436
14437/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
14438#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
14439#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
14440#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
14441#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
14442#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
14443#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
14444
14445/******************** Bit definition for USB_OTG_CID register ********************/
14446#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
14447#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
14448#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
14449
14450/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
14451#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
14452#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
14453#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
14454#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
14455#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
14456#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
14457#define USB_OTG_GLPMCFG_BESL_Pos (2U)
14458#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
14459#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
14460#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
14461#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
14462#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
14463#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
14464#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
14465#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
14466#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
14467#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
14468#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
14469#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
14470#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
14471#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
14472#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
14473#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
14474#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
14475#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
14476#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
14477#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
14478#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
14479#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
14480#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
14481#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
14482#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
14483#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
14484#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
14485#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
14486#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
14487#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
14488#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
14489#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
14490#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
14491#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
14492#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
14493#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
14494#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
14495#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
14496
14497/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
14498#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
14499#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
14500#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
14501#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
14502#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
14503#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
14504#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
14505#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
14506#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
14507#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
14508#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
14509#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
14510#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
14511#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
14512#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
14513#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
14514#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
14515#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
14516#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
14517#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
14518#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
14519#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
14520#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
14521#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
14522#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
14523#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
14524#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
14525
14526/******************** Bit definition for USB_OTG_HPRT register ********************/
14527#define USB_OTG_HPRT_PCSTS_Pos (0U)
14528#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
14529#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
14530#define USB_OTG_HPRT_PCDET_Pos (1U)
14531#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
14532#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
14533#define USB_OTG_HPRT_PENA_Pos (2U)
14534#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
14535#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
14536#define USB_OTG_HPRT_PENCHNG_Pos (3U)
14537#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
14538#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
14539#define USB_OTG_HPRT_POCA_Pos (4U)
14540#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
14541#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
14542#define USB_OTG_HPRT_POCCHNG_Pos (5U)
14543#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
14544#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
14545#define USB_OTG_HPRT_PRES_Pos (6U)
14546#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
14547#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
14548#define USB_OTG_HPRT_PSUSP_Pos (7U)
14549#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
14550#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
14551#define USB_OTG_HPRT_PRST_Pos (8U)
14552#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
14553#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
14554
14555#define USB_OTG_HPRT_PLSTS_Pos (10U)
14556#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
14557#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
14558#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
14559#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
14560#define USB_OTG_HPRT_PPWR_Pos (12U)
14561#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
14562#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
14563
14564#define USB_OTG_HPRT_PTCTL_Pos (13U)
14565#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
14566#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
14567#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
14568#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
14569#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
14570#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
14571
14572#define USB_OTG_HPRT_PSPD_Pos (17U)
14573#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
14574#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
14575#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
14576#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
14577
14578/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
14579#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
14580#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
14581#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
14582#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
14583#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
14584#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
14585#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
14586#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
14587#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
14588#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
14589#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
14590#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
14591#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
14592#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
14593#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
14594#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
14595#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
14596#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
14597#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
14598#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
14599#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
14600#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
14601#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
14602#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
14603#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
14604#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
14605#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
14606#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
14607#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
14608#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
14609#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
14610#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
14611#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
14612
14613/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
14614#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
14615#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
14616#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
14617#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
14618#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
14619#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
14620
14621/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
14622#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
14623#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
14624#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
14625#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
14626#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
14627#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
14628#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
14629#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
14630#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
14631#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
14632#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
14633#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
14634
14635#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
14636#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14637#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
14638#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14639#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14640#define USB_OTG_DIEPCTL_STALL_Pos (21U)
14641#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
14642#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
14643
14644#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
14645#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14646#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
14647#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14648#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14649#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14650#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14651#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
14652#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
14653#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
14654#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
14655#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
14656#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
14657#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
14658#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
14659#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
14660#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
14661#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
14662#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
14663#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
14664#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
14665#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
14666#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
14667#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
14668#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
14669
14670/******************** Bit definition for USB_OTG_HCCHAR register ********************/
14671#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
14672#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
14673#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
14674
14675#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
14676#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
14677#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
14678#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
14679#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
14680#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
14681#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
14682#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
14683#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
14684#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
14685#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
14686#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
14687#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
14688
14689#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
14690#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
14691#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
14692#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
14693#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
14694
14695#define USB_OTG_HCCHAR_MC_Pos (20U)
14696#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
14697#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
14698#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
14699#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
14700
14701#define USB_OTG_HCCHAR_DAD_Pos (22U)
14702#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
14703#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
14704#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
14705#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
14706#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
14707#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
14708#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
14709#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
14710#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
14711#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
14712#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
14713#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
14714#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
14715#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
14716#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
14717#define USB_OTG_HCCHAR_CHENA_Pos (31U)
14718#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
14719#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
14720
14721/******************** Bit definition for USB_OTG_HCSPLT register ********************/
14722
14723#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
14724#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
14725#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
14726#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14727#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14728#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14729#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14730#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14731#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14732#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14733
14734#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
14735#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
14736#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
14737#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14738#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14739#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14740#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14741#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14742#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14743#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14744
14745#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
14746#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14747#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
14748#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14749#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14750#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
14751#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
14752#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
14753#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
14754#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
14755#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
14756
14757/******************** Bit definition for USB_OTG_HCINT register ********************/
14758#define USB_OTG_HCINT_XFRC_Pos (0U)
14759#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
14760#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
14761#define USB_OTG_HCINT_CHH_Pos (1U)
14762#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
14763#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
14764#define USB_OTG_HCINT_AHBERR_Pos (2U)
14765#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
14766#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
14767#define USB_OTG_HCINT_STALL_Pos (3U)
14768#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
14769#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
14770#define USB_OTG_HCINT_NAK_Pos (4U)
14771#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
14772#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
14773#define USB_OTG_HCINT_ACK_Pos (5U)
14774#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
14775#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
14776#define USB_OTG_HCINT_NYET_Pos (6U)
14777#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
14778#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
14779#define USB_OTG_HCINT_TXERR_Pos (7U)
14780#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
14781#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
14782#define USB_OTG_HCINT_BBERR_Pos (8U)
14783#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
14784#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
14785#define USB_OTG_HCINT_FRMOR_Pos (9U)
14786#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
14787#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
14788#define USB_OTG_HCINT_DTERR_Pos (10U)
14789#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
14790#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
14791
14792/******************** Bit definition for USB_OTG_DIEPINT register ********************/
14793#define USB_OTG_DIEPINT_XFRC_Pos (0U)
14794#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
14795#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
14796#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
14797#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
14798#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
14799#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
14800#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
14801#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
14802#define USB_OTG_DIEPINT_TOC_Pos (3U)
14803#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
14804#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
14805#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
14806#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
14807#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
14808#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
14809#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
14810#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
14811#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
14812#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
14813#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
14814#define USB_OTG_DIEPINT_TXFE_Pos (7U)
14815#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
14816#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
14817#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
14818#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
14819#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
14820#define USB_OTG_DIEPINT_BNA_Pos (9U)
14821#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
14822#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
14823#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
14824#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
14825#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
14826#define USB_OTG_DIEPINT_BERR_Pos (12U)
14827#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
14828#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
14829#define USB_OTG_DIEPINT_NAK_Pos (13U)
14830#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
14831#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
14832
14833/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
14834#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
14835#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
14836#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
14837#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
14838#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
14839#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
14840#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
14841#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
14842#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
14843#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
14844#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
14845#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
14846#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
14847#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
14848#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
14849#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
14850#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
14851#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
14852#define USB_OTG_HCINTMSK_NYET_Pos (6U)
14853#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
14854#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
14855#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
14856#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
14857#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
14858#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
14859#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
14860#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
14861#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
14862#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
14863#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
14864#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
14865#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
14866#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
14867
14868/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
14869
14870#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
14871#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
14872#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
14873#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
14874#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
14875#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
14876#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
14877#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
14878#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
14879/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
14880#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
14881#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
14882#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
14883#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
14884#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
14885#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
14886#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
14887#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
14888#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
14889#define USB_OTG_HCTSIZ_DPID_Pos (29U)
14890#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
14891#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
14892#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
14893#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
14894
14895/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
14896#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
14897#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
14898#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
14899
14900/******************** Bit definition for USB_OTG_HCDMA register ********************/
14901#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
14902#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
14903#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
14904
14905/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
14906#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
14907#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
14908#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
14909
14910/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
14911#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
14912#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
14913#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
14914#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
14915#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
14916#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
14917
14918/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
14919
14920#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
14921#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
14922#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
14923#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
14924#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
14925#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
14926#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
14927#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
14928#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
14929#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
14930#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
14931#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
14932#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
14933#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
14934#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
14935#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
14936#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14937#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
14938#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14939#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14940#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
14941#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
14942#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
14943#define USB_OTG_DOEPCTL_STALL_Pos (21U)
14944#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
14945#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
14946#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
14947#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
14948#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
14949#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
14950#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
14951#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
14952#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
14953#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
14954#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
14955#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
14956#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
14957#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
14958
14959/******************** Bit definition for USB_OTG_DOEPINT register ********************/
14960#define USB_OTG_DOEPINT_XFRC_Pos (0U)
14961#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
14962#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
14963#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
14964#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
14965#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
14966#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
14967#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
14968#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
14969#define USB_OTG_DOEPINT_STUP_Pos (3U)
14970#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
14971#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
14972#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
14973#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
14974#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
14975#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
14976#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
14977#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
14978#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
14979#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
14980#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
14981#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
14982#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
14983#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
14984#define USB_OTG_DOEPINT_NAK_Pos (13U)
14985#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
14986#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
14987#define USB_OTG_DOEPINT_NYET_Pos (14U)
14988#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
14989#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
14990#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
14991#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
14992#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
14993/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
14994
14995#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
14996#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
14997#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
14998#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
14999#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
15000#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
15001
15002#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
15003#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
15004#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
15005#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
15006#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
15007
15008/******************** Bit definition for PCGCCTL register ********************/
15009#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
15010#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
15011#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
15012#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
15013#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
15014#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
15015#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
15016#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
15017#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
15018
15019/* Legacy define */
15020/******************** Bit definition for OTG register ********************/
15021#define USB_OTG_CHNUM_Pos (0U)
15022#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
15023#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
15024#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
15025#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
15026#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
15027#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
15028#define USB_OTG_BCNT_Pos (4U)
15029#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
15030#define USB_OTG_BCNT USB_OTG_BCNT_Msk
15031
15032#define USB_OTG_DPID_Pos (15U)
15033#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
15034#define USB_OTG_DPID USB_OTG_DPID_Msk
15035#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
15036#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
15037
15038#define USB_OTG_PKTSTS_Pos (17U)
15039#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
15040#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
15041#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
15042#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
15043#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
15044#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
15045
15046#define USB_OTG_EPNUM_Pos (0U)
15047#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
15048#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
15049#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
15050#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
15051#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
15052#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
15053
15054#define USB_OTG_FRMNUM_Pos (21U)
15055#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
15056#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
15057#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
15058#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
15059#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
15060#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
15064
15068
15072
15073/******************************* ADC Instances ********************************/
15074#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
15075
15076#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
15077
15078/******************************* CAN Instances ********************************/
15079#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
15080 ((INSTANCE) == CAN2) || \
15081 ((INSTANCE) == CAN3))
15082
15083/****************************** DFSDM Instances *******************************/
15084#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
15085 ((INSTANCE) == DFSDM1_Filter1) || \
15086 ((INSTANCE) == DFSDM2_Filter0) || \
15087 ((INSTANCE) == DFSDM2_Filter1) || \
15088 ((INSTANCE) == DFSDM2_Filter2) || \
15089 ((INSTANCE) == DFSDM2_Filter3))
15090
15091#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
15092 ((INSTANCE) == DFSDM1_Channel1) || \
15093 ((INSTANCE) == DFSDM1_Channel2) || \
15094 ((INSTANCE) == DFSDM1_Channel3) || \
15095 ((INSTANCE) == DFSDM2_Channel0) || \
15096 ((INSTANCE) == DFSDM2_Channel1) || \
15097 ((INSTANCE) == DFSDM2_Channel2) || \
15098 ((INSTANCE) == DFSDM2_Channel3) || \
15099 ((INSTANCE) == DFSDM2_Channel4) || \
15100 ((INSTANCE) == DFSDM2_Channel5) || \
15101 ((INSTANCE) == DFSDM2_Channel6) || \
15102 ((INSTANCE) == DFSDM2_Channel7))
15103/******************************* CRC Instances ********************************/
15104#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
15105
15106/******************************* DAC Instances ********************************/
15107#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
15108
15109
15110/******************************** DMA Instances *******************************/
15111#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
15112 ((INSTANCE) == DMA1_Stream1) || \
15113 ((INSTANCE) == DMA1_Stream2) || \
15114 ((INSTANCE) == DMA1_Stream3) || \
15115 ((INSTANCE) == DMA1_Stream4) || \
15116 ((INSTANCE) == DMA1_Stream5) || \
15117 ((INSTANCE) == DMA1_Stream6) || \
15118 ((INSTANCE) == DMA1_Stream7) || \
15119 ((INSTANCE) == DMA2_Stream0) || \
15120 ((INSTANCE) == DMA2_Stream1) || \
15121 ((INSTANCE) == DMA2_Stream2) || \
15122 ((INSTANCE) == DMA2_Stream3) || \
15123 ((INSTANCE) == DMA2_Stream4) || \
15124 ((INSTANCE) == DMA2_Stream5) || \
15125 ((INSTANCE) == DMA2_Stream6) || \
15126 ((INSTANCE) == DMA2_Stream7))
15127
15128/******************************* GPIO Instances *******************************/
15129#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
15130 ((INSTANCE) == GPIOB) || \
15131 ((INSTANCE) == GPIOC) || \
15132 ((INSTANCE) == GPIOD) || \
15133 ((INSTANCE) == GPIOE) || \
15134 ((INSTANCE) == GPIOF) || \
15135 ((INSTANCE) == GPIOG) || \
15136 ((INSTANCE) == GPIOH))
15137
15138/******************************** I2C Instances *******************************/
15139#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
15140 ((INSTANCE) == I2C2) || \
15141 ((INSTANCE) == I2C3))
15142
15143/******************************* SMBUS Instances ******************************/
15144#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
15145
15146/******************************** I2S Instances *******************************/
15147#define IS_I2S_APB1_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
15148 ((INSTANCE) == SPI3))
15149
15150#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
15151 ((INSTANCE) == SPI2) || \
15152 ((INSTANCE) == SPI3) || \
15153 ((INSTANCE) == SPI4) || \
15154 ((INSTANCE) == SPI5))
15155
15156/*************************** I2S Extended Instances ***************************/
15157#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
15158 ((INSTANCE) == I2S3ext))
15159/* Legacy Defines */
15160#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
15161
15162/******************************* AES Instances ********************************/
15163#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
15164
15165/******************************* LPTIM Instances ******************************/
15166#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
15167
15168/******************************* RNG Instances ********************************/
15169#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
15170
15171/****************************** RTC Instances *********************************/
15172#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
15173
15174
15175/******************************** SPI Instances *******************************/
15176
15177#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
15178 ((INSTANCE) == SPI2) || \
15179 ((INSTANCE) == SPI3) || \
15180 ((INSTANCE) == SPI4) || \
15181 ((INSTANCE) == SPI5))
15182
15183
15184/*************************** SPI Extended Instances ***************************/
15185#define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
15186 ((INSTANCE) == SPI2) || \
15187 ((INSTANCE) == SPI3) || \
15188 ((INSTANCE) == SPI4) || \
15189 ((INSTANCE) == SPI5) || \
15190 ((INSTANCE) == I2S2ext) || \
15191 ((INSTANCE) == I2S3ext))
15192/******************************* SAI Instances ********************************/
15193#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
15194 ((PERIPH) == SAI1_Block_B))
15195/****************** TIM Instances : All supported instances *******************/
15196#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15197 ((INSTANCE) == TIM2) || \
15198 ((INSTANCE) == TIM3) || \
15199 ((INSTANCE) == TIM4) || \
15200 ((INSTANCE) == TIM5) || \
15201 ((INSTANCE) == TIM6) || \
15202 ((INSTANCE) == TIM7) || \
15203 ((INSTANCE) == TIM8) || \
15204 ((INSTANCE) == TIM9) || \
15205 ((INSTANCE) == TIM10)|| \
15206 ((INSTANCE) == TIM11)|| \
15207 ((INSTANCE) == TIM12)|| \
15208 ((INSTANCE) == TIM13)|| \
15209 ((INSTANCE) == TIM14))
15210
15211/************* TIM Instances : at least 1 capture/compare channel *************/
15212#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15213 ((INSTANCE) == TIM2) || \
15214 ((INSTANCE) == TIM3) || \
15215 ((INSTANCE) == TIM4) || \
15216 ((INSTANCE) == TIM5) || \
15217 ((INSTANCE) == TIM8) || \
15218 ((INSTANCE) == TIM9) || \
15219 ((INSTANCE) == TIM10) || \
15220 ((INSTANCE) == TIM11) || \
15221 ((INSTANCE) == TIM12) || \
15222 ((INSTANCE) == TIM13) || \
15223 ((INSTANCE) == TIM14))
15224
15225/************ TIM Instances : at least 2 capture/compare channels *************/
15226#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15227 ((INSTANCE) == TIM2) || \
15228 ((INSTANCE) == TIM3) || \
15229 ((INSTANCE) == TIM4) || \
15230 ((INSTANCE) == TIM5) || \
15231 ((INSTANCE) == TIM8) || \
15232 ((INSTANCE) == TIM9) || \
15233 ((INSTANCE) == TIM12))
15234
15235/************ TIM Instances : at least 3 capture/compare channels *************/
15236#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15237 ((INSTANCE) == TIM2) || \
15238 ((INSTANCE) == TIM3) || \
15239 ((INSTANCE) == TIM4) || \
15240 ((INSTANCE) == TIM5) || \
15241 ((INSTANCE) == TIM8))
15242
15243/************ TIM Instances : at least 4 capture/compare channels *************/
15244#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15245 ((INSTANCE) == TIM2) || \
15246 ((INSTANCE) == TIM3) || \
15247 ((INSTANCE) == TIM4) || \
15248 ((INSTANCE) == TIM5) || \
15249 ((INSTANCE) == TIM8))
15250
15251/******************** TIM Instances : Advanced-control timers *****************/
15252#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15253 ((INSTANCE) == TIM8))
15254
15255/******************* TIM Instances : Timer input XOR function *****************/
15256#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15257 ((INSTANCE) == TIM2) || \
15258 ((INSTANCE) == TIM3) || \
15259 ((INSTANCE) == TIM4) || \
15260 ((INSTANCE) == TIM5) || \
15261 ((INSTANCE) == TIM8))
15262
15263/****************** TIM Instances : DMA requests generation (UDE) *************/
15264#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15265 ((INSTANCE) == TIM2) || \
15266 ((INSTANCE) == TIM3) || \
15267 ((INSTANCE) == TIM4) || \
15268 ((INSTANCE) == TIM5) || \
15269 ((INSTANCE) == TIM6) || \
15270 ((INSTANCE) == TIM7) || \
15271 ((INSTANCE) == TIM8))
15272
15273/************ TIM Instances : DMA requests generation (CCxDE) *****************/
15274#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15275 ((INSTANCE) == TIM2) || \
15276 ((INSTANCE) == TIM3) || \
15277 ((INSTANCE) == TIM4) || \
15278 ((INSTANCE) == TIM5) || \
15279 ((INSTANCE) == TIM8))
15280
15281/************ TIM Instances : DMA requests generation (COMDE) *****************/
15282#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15283 ((INSTANCE) == TIM2) || \
15284 ((INSTANCE) == TIM3) || \
15285 ((INSTANCE) == TIM4) || \
15286 ((INSTANCE) == TIM5) || \
15287 ((INSTANCE) == TIM8))
15288
15289/******************** TIM Instances : DMA burst feature ***********************/
15290#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15291 ((INSTANCE) == TIM2) || \
15292 ((INSTANCE) == TIM3) || \
15293 ((INSTANCE) == TIM4) || \
15294 ((INSTANCE) == TIM5) || \
15295 ((INSTANCE) == TIM8))
15296
15297/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
15298#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15299 ((INSTANCE) == TIM2) || \
15300 ((INSTANCE) == TIM3) || \
15301 ((INSTANCE) == TIM4) || \
15302 ((INSTANCE) == TIM5) || \
15303 ((INSTANCE) == TIM6) || \
15304 ((INSTANCE) == TIM7) || \
15305 ((INSTANCE) == TIM8))
15306
15307/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
15308#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15309 ((INSTANCE) == TIM2) || \
15310 ((INSTANCE) == TIM3) || \
15311 ((INSTANCE) == TIM4) || \
15312 ((INSTANCE) == TIM5) || \
15313 ((INSTANCE) == TIM8) || \
15314 ((INSTANCE) == TIM9) || \
15315 ((INSTANCE) == TIM12))
15316/********************** TIM Instances : 32 bit Counter ************************/
15317#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
15318 ((INSTANCE) == TIM5))
15319
15320/***************** TIM Instances : external trigger input available ************/
15321#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15322 ((INSTANCE) == TIM2) || \
15323 ((INSTANCE) == TIM3) || \
15324 ((INSTANCE) == TIM4) || \
15325 ((INSTANCE) == TIM5) || \
15326 ((INSTANCE) == TIM8))
15327
15328/****************** TIM Instances : remapping capability **********************/
15329#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
15330 ((INSTANCE) == TIM5) || \
15331 ((INSTANCE) == TIM11))
15332
15333/******************* TIM Instances : output(s) available **********************/
15334#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
15335 ((((INSTANCE) == TIM1) && \
15336 (((CHANNEL) == TIM_CHANNEL_1) || \
15337 ((CHANNEL) == TIM_CHANNEL_2) || \
15338 ((CHANNEL) == TIM_CHANNEL_3) || \
15339 ((CHANNEL) == TIM_CHANNEL_4))) \
15340 || \
15341 (((INSTANCE) == TIM2) && \
15342 (((CHANNEL) == TIM_CHANNEL_1) || \
15343 ((CHANNEL) == TIM_CHANNEL_2) || \
15344 ((CHANNEL) == TIM_CHANNEL_3) || \
15345 ((CHANNEL) == TIM_CHANNEL_4))) \
15346 || \
15347 (((INSTANCE) == TIM3) && \
15348 (((CHANNEL) == TIM_CHANNEL_1) || \
15349 ((CHANNEL) == TIM_CHANNEL_2) || \
15350 ((CHANNEL) == TIM_CHANNEL_3) || \
15351 ((CHANNEL) == TIM_CHANNEL_4))) \
15352 || \
15353 (((INSTANCE) == TIM4) && \
15354 (((CHANNEL) == TIM_CHANNEL_1) || \
15355 ((CHANNEL) == TIM_CHANNEL_2) || \
15356 ((CHANNEL) == TIM_CHANNEL_3) || \
15357 ((CHANNEL) == TIM_CHANNEL_4))) \
15358 || \
15359 (((INSTANCE) == TIM5) && \
15360 (((CHANNEL) == TIM_CHANNEL_1) || \
15361 ((CHANNEL) == TIM_CHANNEL_2) || \
15362 ((CHANNEL) == TIM_CHANNEL_3) || \
15363 ((CHANNEL) == TIM_CHANNEL_4))) \
15364 || \
15365 (((INSTANCE) == TIM8) && \
15366 (((CHANNEL) == TIM_CHANNEL_1) || \
15367 ((CHANNEL) == TIM_CHANNEL_2) || \
15368 ((CHANNEL) == TIM_CHANNEL_3) || \
15369 ((CHANNEL) == TIM_CHANNEL_4))) \
15370 || \
15371 (((INSTANCE) == TIM9) && \
15372 (((CHANNEL) == TIM_CHANNEL_1) || \
15373 ((CHANNEL) == TIM_CHANNEL_2))) \
15374 || \
15375 (((INSTANCE) == TIM10) && \
15376 (((CHANNEL) == TIM_CHANNEL_1))) \
15377 || \
15378 (((INSTANCE) == TIM11) && \
15379 (((CHANNEL) == TIM_CHANNEL_1))) \
15380 || \
15381 (((INSTANCE) == TIM12) && \
15382 (((CHANNEL) == TIM_CHANNEL_1) || \
15383 ((CHANNEL) == TIM_CHANNEL_2))) \
15384 || \
15385 (((INSTANCE) == TIM13) && \
15386 (((CHANNEL) == TIM_CHANNEL_1))) \
15387 || \
15388 (((INSTANCE) == TIM14) && \
15389 (((CHANNEL) == TIM_CHANNEL_1))))
15390
15391/************ TIM Instances : complementary output(s) available ***************/
15392#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15393 ((((INSTANCE) == TIM1) && \
15394 (((CHANNEL) == TIM_CHANNEL_1) || \
15395 ((CHANNEL) == TIM_CHANNEL_2) || \
15396 ((CHANNEL) == TIM_CHANNEL_3))) \
15397 || \
15398 (((INSTANCE) == TIM8) && \
15399 (((CHANNEL) == TIM_CHANNEL_1) || \
15400 ((CHANNEL) == TIM_CHANNEL_2) || \
15401 ((CHANNEL) == TIM_CHANNEL_3))))
15402
15403/****************** TIM Instances : supporting counting mode selection ********/
15404#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15405 ((INSTANCE) == TIM2) || \
15406 ((INSTANCE) == TIM3) || \
15407 ((INSTANCE) == TIM4) || \
15408 ((INSTANCE) == TIM5) || \
15409 ((INSTANCE) == TIM8))
15410
15411/****************** TIM Instances : supporting clock division *****************/
15412#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15413 ((INSTANCE) == TIM2) || \
15414 ((INSTANCE) == TIM3) || \
15415 ((INSTANCE) == TIM4) || \
15416 ((INSTANCE) == TIM5) || \
15417 ((INSTANCE) == TIM8) || \
15418 ((INSTANCE) == TIM9) || \
15419 ((INSTANCE) == TIM10)|| \
15420 ((INSTANCE) == TIM11)|| \
15421 ((INSTANCE) == TIM12)|| \
15422 ((INSTANCE) == TIM13)|| \
15423 ((INSTANCE) == TIM14))
15424
15425/****************** TIM Instances : supporting commutation event generation ***/
15426#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
15427 ((INSTANCE) == TIM8))
15428
15429
15430/****************** TIM Instances : supporting OCxREF clear *******************/
15431#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15432 ((INSTANCE) == TIM2) || \
15433 ((INSTANCE) == TIM3) || \
15434 ((INSTANCE) == TIM4) || \
15435 ((INSTANCE) == TIM5) || \
15436 ((INSTANCE) == TIM8))
15437
15438/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
15439#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15440 ((INSTANCE) == TIM2) || \
15441 ((INSTANCE) == TIM3) || \
15442 ((INSTANCE) == TIM4) || \
15443 ((INSTANCE) == TIM5) || \
15444 ((INSTANCE) == TIM8) || \
15445 ((INSTANCE) == TIM9) || \
15446 ((INSTANCE) == TIM12))
15447
15448/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
15449#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15450 ((INSTANCE) == TIM2) || \
15451 ((INSTANCE) == TIM3) || \
15452 ((INSTANCE) == TIM4) || \
15453 ((INSTANCE) == TIM5) || \
15454 ((INSTANCE) == TIM8))
15455
15456/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
15457#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15458 ((INSTANCE) == TIM2) || \
15459 ((INSTANCE) == TIM3) || \
15460 ((INSTANCE) == TIM4) || \
15461 ((INSTANCE) == TIM5) || \
15462 ((INSTANCE) == TIM8) || \
15463 ((INSTANCE) == TIM9) || \
15464 ((INSTANCE) == TIM12))
15465
15466/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
15467#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15468 ((INSTANCE) == TIM2) || \
15469 ((INSTANCE) == TIM3) || \
15470 ((INSTANCE) == TIM4) || \
15471 ((INSTANCE) == TIM5) || \
15472 ((INSTANCE) == TIM8) || \
15473 ((INSTANCE) == TIM9) || \
15474 ((INSTANCE) == TIM12))
15475
15476/****************** TIM Instances : supporting repetition counter *************/
15477#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15478 ((INSTANCE) == TIM8))
15479
15480/****************** TIM Instances : supporting encoder interface **************/
15481#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15482 ((INSTANCE) == TIM2) || \
15483 ((INSTANCE) == TIM3) || \
15484 ((INSTANCE) == TIM4) || \
15485 ((INSTANCE) == TIM5) || \
15486 ((INSTANCE) == TIM8) || \
15487 ((INSTANCE) == TIM9))
15488/****************** TIM Instances : supporting Hall sensor interface **********/
15489#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15490 ((INSTANCE) == TIM2) || \
15491 ((INSTANCE) == TIM3) || \
15492 ((INSTANCE) == TIM4) || \
15493 ((INSTANCE) == TIM5) || \
15494 ((INSTANCE) == TIM8))
15495/****************** TIM Instances : supporting the break function *************/
15496#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15497 ((INSTANCE) == TIM8))
15498
15499/******************** USART Instances : Synchronous mode **********************/
15500#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15501 ((INSTANCE) == USART2) || \
15502 ((INSTANCE) == USART3) || \
15503 ((INSTANCE) == USART6))
15504
15505/******************** UART Instances : Half-Duplex mode **********************/
15506#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15507 ((INSTANCE) == USART2) || \
15508 ((INSTANCE) == USART3) || \
15509 ((INSTANCE) == UART4) || \
15510 ((INSTANCE) == UART5) || \
15511 ((INSTANCE) == USART6) || \
15512 ((INSTANCE) == UART7) || \
15513 ((INSTANCE) == UART8) || \
15514 ((INSTANCE) == UART9) || \
15515 ((INSTANCE) == UART10))
15516
15517/* Legacy defines */
15518#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15519
15520/****************** UART Instances : Hardware Flow control ********************/
15521#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15522 ((INSTANCE) == USART2) || \
15523 ((INSTANCE) == USART3) || \
15524 ((INSTANCE) == USART6))
15525/******************** UART Instances : LIN mode **********************/
15526#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
15527
15528/********************* UART Instances : Smart card mode ***********************/
15529#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15530 ((INSTANCE) == USART2) || \
15531 ((INSTANCE) == USART3) || \
15532 ((INSTANCE) == USART6))
15533
15534/*********************** UART Instances : IRDA mode ***************************/
15535#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15536 ((INSTANCE) == USART2) || \
15537 ((INSTANCE) == USART3) || \
15538 ((INSTANCE) == UART4) || \
15539 ((INSTANCE) == UART5) || \
15540 ((INSTANCE) == USART6) || \
15541 ((INSTANCE) == UART7) || \
15542 ((INSTANCE) == UART8) || \
15543 ((INSTANCE) == UART9) || \
15544 ((INSTANCE) == UART10))
15545
15546/*********************** PCD Instances ****************************************/
15547#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
15548
15549/*********************** HCD Instances ****************************************/
15550#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
15551
15552/****************************** SDIO Instances ********************************/
15553#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
15554
15555/****************************** IWDG Instances ********************************/
15556#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
15557
15558/****************************** WWDG Instances ********************************/
15559#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
15560
15561
15562/***************************** FMPI2C Instances *******************************/
15563#define IS_FMPI2C_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FMPI2C1)
15564#define IS_FMPSMBUS_ALL_INSTANCE IS_FMPI2C_ALL_INSTANCE
15565
15566/****************************** QSPI Instances ********************************/
15567#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
15568/****************************** USB Exported Constants ************************/
15569#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
15570#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
15571#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
15572#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
15573
15574/*
15575 * @brief Specific devices reset values definitions
15576 */
15577#define RCC_PLLCFGR_RST_VALUE 0x24003010U
15578#define RCC_PLLI2SCFGR_RST_VALUE 0x24003010U
15579
15580#define RCC_MAX_FREQUENCY 100000000U
15581#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY
15582#define RCC_MAX_FREQUENCY_SCALE2 84000000U
15583#define RCC_MAX_FREQUENCY_SCALE3 64000000U
15584#define RCC_PLLVCO_OUTPUT_MIN 100000000U
15585#define RCC_PLLVCO_INPUT_MIN 950000U
15586#define RCC_PLLVCO_INPUT_MAX 2100000U
15587#define RCC_PLLVCO_OUTPUT_MAX 432000000U
15588
15589#define RCC_PLLN_MIN_VALUE 50U
15590#define RCC_PLLN_MAX_VALUE 432U
15591
15592#define FLASH_SCALE1_LATENCY1_FREQ 30000000U
15593#define FLASH_SCALE1_LATENCY2_FREQ 64000000U
15594#define FLASH_SCALE1_LATENCY3_FREQ 90000000U
15595
15596#define FLASH_SCALE2_LATENCY1_FREQ 30000000U
15597#define FLASH_SCALE2_LATENCY2_FREQ 64000000U
15598
15599#define FLASH_SCALE3_LATENCY1_FREQ 30000000U
15600#define FLASH_SCALE3_LATENCY2_FREQ 64000000U
15601
15602
15606
15610
15614
15615#ifdef __cplusplus
15616}
15617#endif /* __cplusplus */
15618
15619#endif /* __STM32F423xx_H */
__IO
#define __IO
Definition core_armv81mml.h:290
RESERVED
#define RESERVED(N, T)
Definition core_ca.h:179
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f401xc.h:66
PendSV_IRQn
@ PendSV_IRQn
Definition stm32f401xc.h:74
DFSDM2_FLT1_IRQn
@ DFSDM2_FLT1_IRQn
Definition stm32f413xx.h:168
EXTI2_IRQn
@ EXTI2_IRQn
Definition stm32f401xc.h:85
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition stm32f401xc.h:90
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition stm32f405xx.h:99
UART10_IRQn
@ UART10_IRQn
Definition stm32f413xx.h:162
SDIO_IRQn
@ SDIO_IRQn
Definition stm32f401xc.h:116
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition stm32f401xc.h:80
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition stm32f401xc.h:119
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition stm32f401xc.h:126
UART7_IRQn
@ UART7_IRQn
Definition stm32f413xx.h:156
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition stm32f401xc.h:105
UART9_IRQn
@ UART9_IRQn
Definition stm32f413xx.h:161
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition stm32f401xc.h:106
CAN3_SCE_IRQn
@ CAN3_SCE_IRQn
Definition stm32f413xx.h:153
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition stm32f401xc.h:69
SAI1_IRQn
@ SAI1_IRQn
Definition stm32f413xx.h:160
TIM4_IRQn
@ TIM4_IRQn
Definition stm32f401xc.h:103
TIM2_IRQn
@ TIM2_IRQn
Definition stm32f401xc.h:101
DFSDM2_FLT0_IRQn
@ DFSDM2_FLT0_IRQn
Definition stm32f413xx.h:167
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition stm32f401xc.h:127
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition stm32f405xx.h:120
USART2_IRQn
@ USART2_IRQn
Definition stm32f401xc.h:111
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition stm32f401xc.h:122
SVCall_IRQn
@ SVCall_IRQn
Definition stm32f401xc.h:72
ADC_IRQn
@ ADC_IRQn
Definition stm32f401xc.h:95
SPI3_IRQn
@ SPI3_IRQn
Definition stm32f401xc.h:118
SPI2_IRQn
@ SPI2_IRQn
Definition stm32f401xc.h:109
DFSDM2_FLT2_IRQn
@ DFSDM2_FLT2_IRQn
Definition stm32f413xx.h:169
TIM7_IRQn
@ TIM7_IRQn
Definition stm32f405xx.h:132
UART8_IRQn
@ UART8_IRQn
Definition stm32f413xx.h:157
CAN2_SCE_IRQn
@ CAN2_SCE_IRQn
Definition stm32f405xx.h:141
RCC_IRQn
@ RCC_IRQn
Definition stm32f401xc.h:82
CAN3_RX0_IRQn
@ CAN3_RX0_IRQn
Definition stm32f413xx.h:151
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition stm32f405xx.h:131
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition stm32f401xc.h:107
QUADSPI_IRQn
@ QUADSPI_IRQn
Definition stm32f412rx.h:152
DFSDM1_FLT0_IRQn
@ DFSDM1_FLT0_IRQn
Definition stm32f412cx.h:135
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition stm32f405xx.h:123
UsageFault_IRQn
@ UsageFault_IRQn
Definition stm32f401xc.h:71
SysTick_IRQn
@ SysTick_IRQn
Definition stm32f401xc.h:75
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition stm32f401xc.h:130
FMPI2C1_ER_IRQn
@ FMPI2C1_ER_IRQn
Definition stm32f410cx.h:127
CAN3_TX_IRQn
@ CAN3_TX_IRQn
Definition stm32f413xx.h:150
DFSDM2_FLT3_IRQn
@ DFSDM2_FLT3_IRQn
Definition stm32f413xx.h:170
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition stm32f401xc.h:129
AES_IRQn
@ AES_IRQn
Definition stm32f423xx.h:154
CAN2_RX0_IRQn
@ CAN2_RX0_IRQn
Definition stm32f405xx.h:139
BusFault_IRQn
@ BusFault_IRQn
Definition stm32f401xc.h:70
SPI5_IRQn
@ SPI5_IRQn
Definition stm32f410cx.h:125
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition stm32f401xc.h:73
RNG_IRQn
@ RNG_IRQn
Definition stm32f405xx.h:153
FLASH_IRQn
@ FLASH_IRQn
Definition stm32f401xc.h:81
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition stm32f401xc.h:125
WWDG_IRQn
@ WWDG_IRQn
Definition stm32f401xc.h:77
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition stm32f401xc.h:104
TIM3_IRQn
@ TIM3_IRQn
Definition stm32f401xc.h:102
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition stm32f401xc.h:120
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition stm32f405xx.h:96
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition stm32f401xc.h:88
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition stm32f401xc.h:112
SPI4_IRQn
@ SPI4_IRQn
Definition stm32f401xc.h:132
TIM1_UP_TIM10_IRQn
@ TIM1_UP_TIM10_IRQn
Definition stm32f401xc.h:98
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition stm32f401xc.h:96
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition stm32f401xc.h:89
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition stm32f410cx.h:128
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition stm32f401xc.h:124
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition stm32f401xc.h:114
FPU_IRQn
@ FPU_IRQn
Definition stm32f401xc.h:131
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition stm32f405xx.h:121
USART6_IRQn
@ USART6_IRQn
Definition stm32f401xc.h:128
SPI1_IRQn
@ SPI1_IRQn
Definition stm32f401xc.h:108
PVD_IRQn
@ PVD_IRQn
Definition stm32f401xc.h:78
TIM1_TRG_COM_TIM11_IRQn
@ TIM1_TRG_COM_TIM11_IRQn
Definition stm32f401xc.h:99
TIM1_BRK_TIM9_IRQn
@ TIM1_BRK_TIM9_IRQn
Definition stm32f401xc.h:97
CAN2_RX1_IRQn
@ CAN2_RX1_IRQn
Definition stm32f405xx.h:140
EXTI0_IRQn
@ EXTI0_IRQn
Definition stm32f401xc.h:83
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition stm32f405xx.h:97
EXTI4_IRQn
@ EXTI4_IRQn
Definition stm32f401xc.h:87
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition stm32f401xc.h:121
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition stm32f401xc.h:79
UART5_IRQn
@ UART5_IRQn
Definition stm32f405xx.h:130
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition stm32f401xc.h:93
CAN3_RX1_IRQn
@ CAN3_RX1_IRQn
Definition stm32f413xx.h:152
USART1_IRQn
@ USART1_IRQn
Definition stm32f401xc.h:110
EXTI3_IRQn
@ EXTI3_IRQn
Definition stm32f401xc.h:86
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition stm32f401xc.h:68
UART4_IRQn
@ UART4_IRQn
Definition stm32f405xx.h:129
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition stm32f405xx.h:122
EXTI1_IRQn
@ EXTI1_IRQn
Definition stm32f401xc.h:84
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition stm32f401xc.h:123
FMPI2C1_EV_IRQn
@ FMPI2C1_EV_IRQn
Definition stm32f410cx.h:126
TIM5_IRQn
@ TIM5_IRQn
Definition stm32f401xc.h:117
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition stm32f401xc.h:115
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition stm32f401xc.h:92
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition stm32f401xc.h:94
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition stm32f401xc.h:100
CAN2_TX_IRQn
@ CAN2_TX_IRQn
Definition stm32f405xx.h:138
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition stm32f405xx.h:98
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition stm32f401xc.h:91
USART3_IRQn
@ USART3_IRQn
Definition stm32f405xx.h:116
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition stm32f401xc.h:113
DFSDM1_FLT1_IRQn
@ DFSDM1_FLT1_IRQn
Definition stm32f412cx.h:136
ADC_Common_TypeDef
Definition stm32f401xc.h:176
ADC_TypeDef
Analog to Digital Converter.
Definition stm32f401xc.h:152
AES_TypeDef
AES hardware accelerator.
Definition stm32f423xx.h:771
AES_TypeDef::SUSP3R
__IO uint32_t SUSP3R
Definition stm32f423xx.h:791
AES_TypeDef::IVR2
__IO uint32_t IVR2
Definition stm32f423xx.h:782
AES_TypeDef::SUSP7R
__IO uint32_t SUSP7R
Definition stm32f423xx.h:795
AES_TypeDef::KEYR1
__IO uint32_t KEYR1
Definition stm32f423xx.h:777
AES_TypeDef::IVR1
__IO uint32_t IVR1
Definition stm32f423xx.h:781
AES_TypeDef::IVR3
__IO uint32_t IVR3
Definition stm32f423xx.h:783
AES_TypeDef::KEYR0
__IO uint32_t KEYR0
Definition stm32f423xx.h:776
AES_TypeDef::SUSP5R
__IO uint32_t SUSP5R
Definition stm32f423xx.h:793
AES_TypeDef::IVR0
__IO uint32_t IVR0
Definition stm32f423xx.h:780
AES_TypeDef::DOUTR
__IO uint32_t DOUTR
Definition stm32f423xx.h:775
AES_TypeDef::KEYR2
__IO uint32_t KEYR2
Definition stm32f423xx.h:778
AES_TypeDef::SUSP1R
__IO uint32_t SUSP1R
Definition stm32f423xx.h:789
AES_TypeDef::KEYR5
__IO uint32_t KEYR5
Definition stm32f423xx.h:785
AES_TypeDef::SUSP6R
__IO uint32_t SUSP6R
Definition stm32f423xx.h:794
AES_TypeDef::SUSP2R
__IO uint32_t SUSP2R
Definition stm32f423xx.h:790
AES_TypeDef::SUSP0R
__IO uint32_t SUSP0R
Definition stm32f423xx.h:788
AES_TypeDef::CR
__IO uint32_t CR
Definition stm32f423xx.h:772
AES_TypeDef::DINR
__IO uint32_t DINR
Definition stm32f423xx.h:774
AES_TypeDef::KEYR3
__IO uint32_t KEYR3
Definition stm32f423xx.h:779
AES_TypeDef::SUSP4R
__IO uint32_t SUSP4R
Definition stm32f423xx.h:792
AES_TypeDef::KEYR6
__IO uint32_t KEYR6
Definition stm32f423xx.h:786
AES_TypeDef::SR
__IO uint32_t SR
Definition stm32f423xx.h:773
AES_TypeDef::KEYR4
__IO uint32_t KEYR4
Definition stm32f423xx.h:784
AES_TypeDef::KEYR7
__IO uint32_t KEYR7
Definition stm32f423xx.h:787
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition stm32f405xx.h:225
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition stm32f405xx.h:237
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition stm32f405xx.h:213
CAN_TypeDef
Controller Area Network.
Definition stm32f405xx.h:247
CRC_TypeDef
CRC calculation unit.
Definition stm32f401xc.h:188
DAC_TypeDef
Digital to Analog Converter.
Definition stm32f405xx.h:290
DBGMCU_TypeDef
Debug MCU.
Definition stm32f401xc.h:201
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition stm32f412cx.h:308
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition stm32f412cx.h:286
DMA_Stream_TypeDef
DMA Controller.
Definition stm32f401xc.h:214
DMA_TypeDef
Definition stm32f401xc.h:224
EXTI_TypeDef
External Interrupt/Event Controller.
Definition stm32f401xc.h:236
FLASH_TypeDef
FLASH Registers.
Definition stm32f401xc.h:250
FMPI2C_TypeDef
Inter-integrated Circuit Interface.
Definition stm32f410cx.h:333
FSMC_Bank1_TypeDef
Flexible Static Memory Controller.
Definition stm32f405xx.h:378
FSMC_Bank1E_TypeDef
Flexible Static Memory Controller Bank1E.
Definition stm32f405xx.h:387
GPIO_TypeDef
General Purpose I/O.
Definition stm32f401xc.h:265
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition stm32f401xc.h:295
IWDG_TypeDef
Independent WATCHDOG.
Definition stm32f401xc.h:313
LPTIM_TypeDef
LPTIMER.
Definition stm32f410cx.h:542
PWR_TypeDef
Power Control.
Definition stm32f401xc.h:326
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition stm32f412rx.h:633
RCC_TypeDef
Reset and Clock Control.
Definition stm32f401xc.h:336
RNG_TypeDef
RNG.
Definition stm32f405xx.h:688
RTC_TypeDef
Real-Time Clock.
Definition stm32f401xc.h:376
SAI_Block_TypeDef
Definition stm32f413xx.h:633
SAI_TypeDef
Serial Audio Interface.
Definition stm32f413xx.h:628
SDIO_TypeDef
SD host Interface.
Definition stm32f401xc.h:424
SPI_TypeDef
Serial Peripheral Interface.
Definition stm32f401xc.h:452
SYSCFG_TypeDef
System configuration controller.
Definition stm32f401xc.h:282
TIM_TypeDef
TIM.
Definition stm32f401xc.h:470
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition stm32f401xc.h:499
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition stm32f401xc.h:548
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition stm32f401xc.h:523
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition stm32f401xc.h:618
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition stm32f401xc.h:604
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition stm32f401xc.h:575
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition stm32f401xc.h:590
WWDG_TypeDef
Window WATCHDOG.
Definition stm32f401xc.h:514
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
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